NEC Cooktop 30500A User Manual

DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD30500, 30500A, 30500B  
VR5000TM, VR5000ATM, VR5000BTM  
64-BIT MICROPROCESSOR  
DESCRIPTION  
Note  
Note  
The µPD30500 (VR5000), µPD30500A  
(VR5000A), and µPD30500B  
(VR5000B) are a high-performance,  
64-bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed  
TM  
by MIPS  
Technologies Inc.  
TM  
The instructions of the VR5000, VR5000A, and VR5000B are compatible with those of the VR3000  
series and  
TM  
TM  
VR4000 series and higher, and completely compatible with those of the VR10000 . Therefore, present applications  
can be used as they are.  
Note Under development  
Detailed functions are descrided in the following manual. Be sure to read the manual when  
designing your system.  
• VR5000 User’s Manual (U11761E)  
FEATURES  
Employs 64-bit MIPS-based RISC architecture  
High-speed processing  
2-way super scalar 5-stage pipeline  
5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (µPD30500)  
6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (µPD30500A)  
8 SPECint95, 8 SPECfp95, 423 MIPS (µPD30500B)  
High-speed translation buffer mechanism (TLB) (48 entries)  
Address space Physical: 36 bits, Virtual: 40 bits  
Floating-point unit (FPU)  
Sum-of-products operation instruction supported  
Primary cache memory (instruction/data: 32K bytes each)  
Secondary cache controller  
Maximum operating frequency Internal : 200MHz (µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B)  
External: 100 MHz  
External/internal multiple selectable from two to eight  
Instruction set compatible with VR3000 and VR4000 series and higher (conforms to MIPS I, II, III, and IV)  
Supply voltage: 3.3 V ±5% (µPD30500)  
Core: 2.5 V ±5%, I/O: 3.3 V ±5% (µPD30500A)  
Core: 1.8 V ±0.1 V, I/O: 3.3 V ±5% (µPD30500B)  
Unless otherwise specified, the VR5000 (µPD30500) is treated as the representative model throughout this  
document.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for availability  
and additional information.  
The mark shows major revised points.  
Document No. U12031EJ3V0DS00 (3rd edition)  
Date Published August 1999 N CP(K)  
Printed in Japan  
1997,1999  
©
 
1997  
MIPS Technologies Inc.  
©
µPD30500, 30500A, 30500B  
PIN CONFIGURATION  
223-pin ceramic PGA (48 × 48 mm)  
µPD30500RJ-150  
µPD30500RJ-180  
µPD30500RJ-200  
Bottom View  
Top View  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
V U T R P N M L K J H G F E D C B A  
A B C D E F G H J K L M N P R T U V  
Index mark  
Data Sheet U12031EJ3V0DS00  
3
 
µPD30500, 30500A, 30500B  
No.  
A2  
Name  
No.  
C5  
Name  
SysADC6  
SysAD16  
SysAD50  
SysAD22  
SysAD24  
SysAD28  
SysAD62  
SysAD44  
SysAD10  
SysAD38  
SysAD4  
SysAD34  
SysAD2  
GND  
No.  
E18  
F1  
Name  
No.  
K17  
K18  
L1  
Name  
GNDP  
No.  
R6  
Name  
SysAD51  
SysAD55  
SysAD27  
SysAD31  
SysAD43  
SysAD39  
SysAD35  
SysAD1  
ScWord1  
ScLine0  
ScLine3  
ScLine6  
GND  
No.  
U9  
Name  
SysAD63  
SysAD13  
SysAD11  
SysAD9  
SysAD37  
SysAD3  
ScWord0  
VDD  
VDD  
VDD  
A3  
GND  
C6  
VDD  
GND  
R7  
U10  
U11  
U12  
U13  
U14  
U15  
U16  
U17  
U18  
V1  
A4  
VDD  
C7  
F2  
Reserved  
ScValid  
Int1  
GND  
R8  
A5  
GND  
C8  
F3  
L2  
SysCmd8  
SysCmd7  
SysCmd5  
ScLine12  
ScLine14  
ScLine15  
VDD  
R9  
A6  
GND  
C9  
F4  
L3  
R10  
R11  
R12  
R13  
R14  
R15  
R16  
R17  
R18  
T1  
A7  
VDD  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
D1  
F15  
F16  
F17  
F18  
G1  
ScDCE0  
ScCWE0  
ScTDE  
GND  
L4  
A8  
GND  
L15  
L16  
L17  
L18  
M1  
A9  
VDD  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
B1  
GND  
GND  
VDD  
GND  
GND  
GND  
G2  
Reserved  
Reserved  
Reserved  
ScCLR  
ScTCE  
Modeln  
VDD  
VDD  
GND  
VDD  
G3  
M2  
SysCmd6  
SysCmd4  
SysCmd1  
ScLine8  
ScLine10  
ScLine13  
GND  
V2  
GND  
GND  
G4  
M3  
V3  
VDD  
GND  
G15  
G16  
G17  
G18  
H1  
M4  
GND  
V4  
GND  
VDD  
GND  
M15  
M16  
M17  
M18  
N1  
T2  
SysAD15  
SysAD47  
SysAD17  
SysAD19  
SysAD23  
SysAD57  
SysAD29  
VDD  
V5  
GND  
GND  
D2  
Int3  
T3  
V6  
VDD  
GND  
D3  
Int5  
T4  
V7  
GND  
GND  
D4  
Release  
VDD  
VDD  
T5  
V8  
VDD  
B2  
GND  
D5  
H2  
Reserved  
Reserved  
Reserved  
VDDOk  
GND  
T6  
V9  
GND  
B3  
VDD  
D6  
SysADC2  
SysAD48  
SysAD52  
SysAD56  
SysAD60  
SysAD14  
SysAD42  
SysAD8  
SysAD36  
H3  
N2  
SysCmd3  
SysCmd2  
SysADC7  
ScLine5  
ScLine7  
ScLine11  
VDD  
T7  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
VDD  
B4  
SysADC4  
SysADC0  
SysAD18  
SysAD20  
SysAD54  
SysAD26  
SysAD58  
SysAD30  
SysAD46  
SysAD12  
SysAD40  
SysAD6  
GND  
D7  
H4  
N3  
T8  
GND  
B5  
D8  
H15  
H16  
H17  
H18  
J1  
N4  
T9  
VDD  
B6  
D9  
ModeClock N15  
T10  
T11  
T12  
T13  
T14  
T15  
SysAD45  
SysAD41  
SysAD7  
SysAD5  
SysAD33  
Reset  
GND  
B7  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
E1  
SysClock  
GND  
N16  
N17  
N18  
P1  
VDD  
B8  
GND  
B9  
GND  
GND  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
C1  
J2  
WrRdy  
Validln  
ExtRqst  
Reserved  
Reserved  
Reserved  
VDD  
VDD  
VDD  
J3  
P2  
SysCmd0  
GND  
ColdReset J4  
P3  
SysCmdP T16  
ScLine1  
VDD  
SysAD0  
ScTOE  
VDD  
J15  
P4  
SysADC1  
ScLine2  
ScLine4  
ScLine9  
GND  
T17  
T18  
U1  
U2  
U3  
U4  
U5  
U6  
J16  
J17  
J18  
K1  
P15  
P16  
P17  
P18  
R1  
VDD  
VDD  
GND  
VDD  
VDD  
E2  
Int0  
VDD  
GND  
VDD  
E3  
Int2  
K2  
ScMatch  
RdRdy  
ScDOE  
Reserved  
VDDP  
VDD  
SysAD21  
SysAD53  
SysAD25  
SysAD59  
SysAD61  
VDD  
E4  
Int4  
K3  
R2  
SysADC5  
SysADC3  
C2  
VDD  
E15  
E16  
E17  
SysAD32  
ScDCE1  
ScCWE1  
K4  
R3  
C3  
ValidOut  
NMI  
K15  
K16  
R4  
BigEndian U7  
SysAD49 U8  
C4  
R5  
Data Sheet U12031EJ3V0DS00  
 
4
µPD30500, 30500A, 30500B  
272-pin plastic BGA (29 × 29 mm)  
µPD30500S2-150  
µPD30500S2-180  
µPD30500S2-200  
µPD30500AS2-200Note  
µPD30500AS2-250Note  
µPD30500BS2-250Note  
µPD30500BS2-300Note  
Bottom View  
Top View  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
AA Y W V U T R P N M L K J H G F E D C B A  
A B C D E F G H J K L M N P R T U V W Y AA  
Note Under development  
Data Sheet U12031EJ3V0DS00  
5
 
µPD30500, 30500A, 30500B  
(1) µPD30500  
No.  
A1  
Name  
GND  
No.  
C5  
Name  
No.  
F1  
Name  
SysAD8  
SysAD38  
SysAD6  
GND  
No.  
Name  
No.  
Name  
No.  
Y1  
Name  
L20  
L21  
M1  
SysAD63  
GND  
ScDCE1  
ScDCE0  
ScCWE0  
ScTCE  
Modeln  
Reserved  
GNDP  
Reserved  
ScLine13  
ScLine11  
ScLine8  
ScLine5  
ScLine4  
ScLine0  
Reset  
VDD  
U18  
U19  
U20  
U21  
V1  
VDD  
VDD  
F2  
A2  
VDD  
C6  
SysAD17  
SysAD49  
GND  
Y2  
VDD  
F3  
SysAD26  
SysAD56  
SysAD24  
VDD  
A3  
GND  
C7  
Y3  
VDD  
F4  
M2  
A4  
SysAD32  
GND  
C8  
Y4  
Release  
Int3  
F18  
F19  
F20  
F21  
G1  
GND  
M3  
A5  
C9  
VDD  
Y5  
SysAD1  
SysAD33  
SysAD3  
GND  
M4  
A6  
ScCWE1  
GND  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
D1  
V2  
VDD  
Y6  
Int2  
M18  
M19  
M20  
M21  
N1  
VDD  
A7  
V3  
VDD  
Y7  
ScValid  
Reserved  
Reserved  
Reserved  
ExtRqst  
RdRdy  
SysCmd8  
SysCmd5  
SysCmd3  
SysCmd0  
SysCmdP  
SysADC1  
SysAD15  
VDD  
SysAD29  
SysAD61  
SysAD31  
GND  
A8  
VDDOk  
GND  
V4  
GND  
Y8  
A9  
V5  
NMI  
Y9  
G2  
SysAD10  
SysAD40  
VDD  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
B1  
SysClock  
GND  
V6  
GND  
Y10  
Y11  
Y12  
Y13  
Y14  
Y15  
Y16  
Y17  
Y18  
Y19  
Y20  
Y21  
AA1  
AA2  
AA3  
AA4  
AA5  
AA6  
AA7  
AA8  
AA9  
G3  
V7  
VDD  
G4  
N2  
SysAD54  
SysAD22  
GND  
ScLine15  
GND  
V8  
VDD  
G18  
G19  
G20  
G21  
H1  
VDD  
N3  
V9  
GND  
SysAD35  
SysAD5  
GND  
N4  
ScLine12  
GND  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
V21  
W1  
VDD  
N18  
N19  
N20  
N21  
P1  
GND  
VDD  
SysAD27  
SysAD59  
GND  
ScLine7  
GND  
VDD  
SysAD42  
SysAD44  
SysAD12  
VDD  
GND  
GND  
H2  
ScLine2  
GND  
VDD  
VDD  
H3  
SysAD50  
SysAD52  
SysAD20  
VDD  
D2  
VDD  
VDD  
H4  
P2  
VDD  
D3  
VDD  
GND  
H18  
H19  
H20  
H21  
J1  
VDD  
P3  
GND  
D4  
GND  
VDD  
VDD  
SysAD7  
SysAD39  
SysAD37  
GND  
P4  
VDD  
D5  
VDD  
GND  
GND  
P18  
P19  
P20  
P21  
R1  
VDD  
B2  
VDD  
D6  
GND  
VDD  
VDD  
SysAD25  
SysAD57  
SysAD55  
GND  
B3  
VDD  
D7  
VDD  
VDD  
GND  
B4  
SysAD2  
SysAD0  
ScTOE  
ScCLR  
ScTDE  
D8  
VDD  
VDD  
ValidOut  
GND  
J2  
SysAD46  
SysAD14  
GND  
B5  
D9  
GND  
GND  
J3  
B6  
D10  
D11  
D12  
VDD  
W2  
VDD  
Int0  
J4  
R2  
SysAD18  
SysAD48  
VDD  
B7  
VDDP  
W3  
VDD  
GND  
J18  
J19  
J20  
J21  
K1  
GND  
R3  
B8  
VDD  
W4  
VDD  
Reserved  
GND  
SysAD9  
SysAD41  
GND  
R4  
B9  
ModeClock D13  
GND  
W5  
Int5  
R18  
R19  
R20  
R21  
T1  
VDD  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
C1  
Reserved  
Reserved  
NC  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
E1  
VDD  
W6  
Int4  
AA10 WrRdy  
AA11 GND  
SysAD53  
SysAD23  
GND  
VDD  
W7  
Int1  
SysAD60  
SysAD30  
SysAD62  
VDD  
GND  
W8  
Reserved  
Reserved  
Reserved  
Validln  
ScDOE  
SysCmd7  
SysCmd4  
SysCmd1  
SysADC7  
SysADC5  
SysAD47  
BigEndian  
VDD  
AA12 ScMatch  
AA13 GND  
K2  
ScLine14  
ScLine10  
ScLine9  
ScLine6  
ScLine3  
ScLine1  
VDD  
VDD  
W9  
K3  
SysAD16  
SysADC0  
SysADC2  
GND  
GND  
W10  
W11  
W12  
W13  
W14  
W15  
W16  
W17  
W18  
W19  
W20  
W21  
AA14 SysCmd6  
AA15 GND  
K4  
T2  
VDD  
K18  
K19  
K20  
K21  
L1  
VDD  
T3  
VDD  
AA16 SysCmd2  
AA17 GND  
SysAD11  
SysAD43  
SysAD13  
GND  
T4  
VDD  
T18  
T19  
T20  
T21  
U1  
GND  
GND  
AA18 SysADC3  
AA19 GND  
SysAD19  
SysAD51  
SysAD21  
GND  
E2  
SysAD36  
SysAD4  
VDD  
VDD  
E3  
AA20 VDD  
L2  
SysAD58  
SysAD28  
VDD  
VDD  
E4  
AA21 GND  
L3  
GND  
E18  
E19  
VDD  
L4  
U2  
SysADC4  
SysADC6  
VDD  
C2  
VDD  
ScWord1  
ScWord0  
GND  
L18  
L19  
VDD  
U3  
C3  
ColdReset E20  
SysAD34 E21  
SysAD45  
U4  
C4  
GND  
Data Sheet U12031EJ3V0DS00  
 
6
µPD30500, 30500A, 30500B  
(2) µPD30500A, 30500B  
No.  
A1  
Name  
GND  
No.  
C5  
Name  
No.  
F1  
Name  
No.  
Name  
No.  
Name  
No.  
Y1  
Name  
VDDIO  
ScDCE1  
ScDCE0  
ScCWE0  
ScTCE  
Modeln  
NC  
SysAD8  
SysAD38  
SysAD6  
GND  
L20  
L21  
M1  
SysAD63  
GND  
U18  
U19  
U20  
U21  
V1  
VDD  
A2  
VDDIO  
Y2  
VDDIO  
C6  
F2  
SysAD17  
SysAD49  
GND  
A3  
GND  
Y3  
VDDIO  
C7  
F3  
SysAD26  
SysAD56  
SysAD24  
VDDIO  
A4  
SysAD32  
GND  
Y4  
Release  
Int3  
C8  
F4  
M2  
A5  
Y5  
C9  
F18  
F19  
F20  
F21  
G1  
GND  
M3  
VDD  
A6  
ScCWE1  
GND  
Y6  
Int2  
C10  
C11  
C12  
C13  
C14  
C15  
C16  
C17  
C18  
C19  
C20  
C21  
D1  
SysAD1  
SysAD33  
SysAD3  
GND  
M4  
V2  
VDD  
A7  
Y7  
ScValid  
GND  
GNDP  
GND  
M18  
M19  
M20  
M21  
N1  
VDDIO  
V3  
VDD  
A8  
VDDOk  
GND  
Y8  
SysAD29  
SysAD61  
SysAD31  
GND  
V4  
GND  
A9  
Y9  
GND  
ScLine13  
ScLine11  
ScLine8  
ScLine5  
ScLine4  
ScLine0  
Reset  
VDDIO  
GND  
V5  
NMI  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
B1  
SysClock  
GND  
Y10  
Y11  
Y12  
Y13  
Y14  
Y15  
Y16  
Y17  
Y18  
Y19  
Y20  
Y21  
AA1  
AA2  
AA3  
AA4  
AA5  
AA6  
AA7  
AA8  
AA9  
GND  
G2  
SysAD10  
SysAD40  
VDDIO  
V6  
GND  
ExtRqst  
RdRdy  
SysCmd8  
SysCmd5  
SysCmd3  
SysCmd0  
SysCmdP  
SysADC1  
SysAD15  
VDDIO  
G3  
V7  
VDD  
ScLine15  
GND  
G4  
N2  
SysAD54  
SysAD22  
GND  
V8  
VDDIO  
GND  
G18  
G19  
G20  
G21  
H1  
VDDIO  
N3  
V9  
ScLine12  
GND  
SysAD35  
SysAD5  
GND  
N4  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
V21  
W1  
VDD  
N18  
N19  
N20  
N21  
P1  
GND  
VDDIO  
VDD  
ScLine7  
GND  
SysAD27  
SysAD59  
GND  
SysAD42  
SysAD44  
SysAD12  
VDD  
GND  
ScLine2  
GND  
VDD  
H2  
VDDIO  
VDD  
D2  
VDD  
H3  
SysAD50  
SysAD52  
SysAD20  
VDD  
VDDIO  
D3  
VDD  
H4  
P2  
GND  
GND  
VDDIO  
D4  
GND  
H18  
H19  
H20  
H21  
J1  
VDD  
P3  
VDDIO  
GND  
VDDIO  
GND  
D5  
VDD  
SysAD7  
SysAD39  
SysAD37  
GND  
P4  
B2  
VDDIO  
VDDIO  
D6  
GND  
P18  
P19  
P20  
P21  
R1  
VDD  
VDD  
B3  
VDDIO  
GND  
D7  
VDDIO  
VDD  
SysAD25  
SysAD57  
SysAD55  
GND  
VDD  
B4  
SysAD2  
SysAD0  
ScTOE  
ScCLR  
ScTDE  
ModeClock  
GND  
ValidOut  
GND  
D8  
VDD  
B5  
D9  
GND  
J2  
SysAD46  
SysAD14  
GND  
GND  
B6  
Int0  
D10  
D11  
D12  
D13  
D14  
D15  
D16  
D17  
D18  
D19  
D20  
D21  
E1  
VDDIO  
VDDP  
J3  
W2  
VDDIO  
VDDIO  
VDDIO  
Int5  
B7  
GND  
J4  
R2  
SysAD18  
SysAD48  
VDDIO  
W3  
B8  
GND  
VDD  
J18  
J19  
J20  
J21  
K1  
GND  
R3  
W4  
B9  
GND  
GND  
SysAD9  
SysAD41  
GND  
R4  
W5  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
B18  
B19  
B20  
B21  
C1  
AA10 WrRdy  
AA11 GND  
VDDIO  
VDD  
R18  
R19  
R20  
R21  
T1  
VDDIO  
W6  
Int4  
GND  
SysAD53  
SysAD23  
GND  
W7  
Int1  
GND  
AA12 ScMatch  
AA13 GND  
GND  
SysAD60  
SysAD30  
SysAD62  
VDDIO  
W8  
GND  
ScLine14  
ScLine10  
ScLine9  
ScLine6  
ScLine3  
ScLine1  
VDDIO  
VDDIO  
GND  
K2  
W9  
GND  
AA14 SysCmd6  
AA15 GND  
K3  
SysAD16  
SysADC0  
SysADC2  
GND  
W10  
W11  
W12  
W13  
W14  
W15  
W16  
W17  
W18  
W19  
W20  
W21  
VDD  
VDD  
K4  
T2  
Validln  
ScDOE  
SysCmd7  
SysCmd4  
SysCmd1  
SysADC7  
SysADC5  
SysAD47  
BigEndian  
VDDIO  
GND  
AA16 SysCmd2  
AA17 GND  
VDD  
K18  
K19  
K20  
K21  
L1  
VDDIO  
T3  
VDD  
SysAD11  
SysAD43  
SysAD13  
GND  
T4  
AA18 SysADC3  
AA19 GND  
GND  
T18  
T19  
T20  
T21  
U1  
GND  
E2  
SysAD36  
SysAD4  
VDD  
SysAD19  
SysAD51  
SysAD21  
GND  
VDDIO  
AA20 VDDIO  
AA21 GND  
E3  
VDDIO  
E4  
L2  
SysAD58  
SysAD28  
VDD  
GND  
E18  
E19  
E20  
E21  
VDD  
L3  
C2  
VDDIO  
ScWord1  
ScWord0  
GND  
L4  
U2  
SysADC4  
SysADC6  
VDD  
C3  
ColdReset  
SysAD34  
L18  
L19  
VDD  
U3  
C4  
SysAD45  
U4  
Data Sheet U12031EJ3V0DS00  
 
7
µPD30500, 30500A, 30500B  
PIN NAMES  
BigEndian  
ColdReset  
ExtRqst  
GND  
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
Endian Mode Select  
Cold Reset  
External Request  
Ground  
GNDP  
Quiet GND for PLL  
Int (0:5)  
ModeClock  
Modeln  
Interrupt Request  
Boot Mode Clock  
Boot Mode Data In  
NC  
No Connection  
NMI  
Non-maskable Interrupt Request  
Read Ready  
RdRdy  
Release  
Reset  
Release Interface  
Reset  
ScCLR  
Secondary Cache Block Clear  
Secondary Cache Write Enable  
Data RAM Chip Enable  
Data RAM Output Enable  
Secondary Cache Line Index  
Secondary Cache Tag Match  
Secondary Cache Tag RAM Chip Enable  
Secondary Cache Tag RAM Data Enable  
Secondary Cache Tag RAM Output Enable  
Secondary Cache Valid  
Secondary Cache Word Index  
System Address/Data Bus  
System Address/Data Check Bus  
System Clock  
ScCWE (0:1)  
ScDCE (0:1)  
ScDOE  
ScLine (0:15)  
ScMatch  
ScTCE  
ScTDE  
ScTOE  
ScValid  
ScWord (0:1)  
SysAD (0:63)  
SysADC (0:7)  
SysClock  
SysCmd (0:8)  
SysCmdP  
Validln  
System Command/Data Identifier  
System Command/Data Identifier Bus Parity  
Valid Input  
ValidOut  
VDD  
Valid Output  
Power Supply (µPD30500)  
Power Supply for Processor Core (µPD30500A, 30500B)  
Power Supply for Processor I/O (µPD30500A, 30500B only)  
VDD is OK  
VDD  
VDDIO  
VDDOk  
VDDP  
Quiet VDD for PLL  
Write Ready  
WrRdy  
Data Sheet U12031EJ3V0DS00  
8
 
µPD30500, 30500A, 30500B  
INTERNAL BLOCK DIAGRAM  
Data, address Control  
System interface  
SysClock  
Clock  
generator  
Instruction cache  
Data cache  
CP0  
TLB  
Execution unit  
Instruction address  
Pipeline control  
Floating-point unit  
Data Sheet U12031EJ3V0DS00  
 
9
µPD30500, 30500A, 30500B  
PIN FUNCTIONS  
Pin Name  
I/O  
I/O  
Function  
SysAD (0:63)  
System address/data bus.  
64-bit bus for communication between processor, secondary cache and external agent.  
SysADC (0:7)  
SysCmd (0:8)  
I/O  
I/O  
System address/data check bus.  
8-bit bus including check bits for the SysAD bus.  
System command/data ID bus.  
9-bit bus for communication of commands and data identifiers between processor  
and external agent.  
SysCmdP  
I/O  
System command/data ID bus parity.  
1-bit even number parity bit for the SysCmd bus.  
ValidIn  
Input  
Valid in.  
Signal indicating that external agent has transmitted valid address or data onto  
SysAD bus and valid command or data identifier onto SysCmd bus.  
ValidOut  
Output Valid out.  
Signal indicating that processor has transmitted valid address or data onto SysAD  
bus and valid command or data identifier onto SysCmd bus.  
ExtRqst  
Input  
External request.  
Signal used by external agent to request for its use by system interface.  
Release  
WrRdy  
Output Interface release.  
Signal indicating that the processor has released the system interface to the slave state.  
Output Write ready.  
Signal indicating that the external agent can accept a processor write request.  
RdRdy  
Input  
Read ready.  
Signal indicating that external agent can accept a processor read request.  
ScCLR  
Output Secondary cache block clear.  
Clears all the valid bits of the tag RAM.  
ScCWE (0:1)  
ScDCE (0:1)  
ScDOE  
Output Secondary cache write enable.  
Write enable signal for the secondary cache RAM.  
Output Data RAM chip select.  
Chip select signal for secondary cache RAM.  
Input  
Data RAM output enable.  
Data output enable signal from the external agent.  
ScLine (0:15)  
ScMatch  
ScTCE  
Output Secondary cache line index.  
Cache line index output of the secondary cache.  
Input  
Secondary cache tag match.  
Tag match signal from secondary cache tag RAM.  
Output Secondary cache tag RAM chip select.  
Chip select signal of the secondary cache tag RAM.  
ScTDE  
Output Secondary cache tag RAM data enable.  
Data enable signal from the secondary cache tag RAM.  
ScTOE  
Output Secondary cache tag RAM output enable.  
Output enable signal from the secondary cache tag RAM.  
ScWord (0:1)  
ScValid  
I/O  
Secondary cache word index.  
Signal indicating that the double word of the secondary cache index is correct.  
I/O  
Secondary cache valid.  
Signal indicating that the data of the secondary cache is valid.  
Data Sheet U12031EJ3V0DS00  
10  
 
µPD30500, 30500A, 30500B  
Pin Name  
Int (0:5)  
I/O  
Function  
Input  
Interrupt.  
General-purpose processor interrupt requests whose input statuses can be confirmed by  
bits 15 through 10 of cause register.  
NMI  
Input  
Input  
Non-maskable interrupt.  
Interrupt request that cannot be masked.  
ColdReset  
Cold reset.  
Signal initializing the internal status of the processor. Inactivate this signal in synchroniza-  
tion with SysClock.  
Reset  
Input  
Reset.  
Signal generating a reset exception, without initializing the internal status of the processor.  
Inactivate this signal in synchronization with SysClock.  
SysClock  
BigEndian  
Input  
Input  
System clock.  
Clock input signal to processor.  
Endian mode setting.  
This signal sets the endian mode of the system interface.  
When setting the endian mode with this signal, specify little endian with the data from the  
ModeIn pin that is input at reset.  
To set the endian mode with the data from the ModeIn pin, fix this signal to 0.  
BigEndian  
Bit 8 of boot mode  
Mode  
1
1
0
0
1
0
1
0
Big endian  
Big endian  
Little endian  
ModeClock  
Modeln  
Output Boot mode clock.  
Successive boot mode data clock output resulting from dividing SysClock by 256.  
Input  
Input  
Boot mode data input.  
Input of initialization bit stream.  
Note  
VDDOk  
VDD and VDDIO  
are valid.  
Signal indicating that the voltage supplied to the VR5000 is 3.135 V or higher for 100 ms,  
and that that status is stabilized. When VDDOk is asserted active, the VR5000 starts an  
initialization sequence.  
VDDP  
GNDP  
VDD  
PLL VDD.  
Power supply for internal PLL.  
PLL GND.  
Ground for internal PLL.  
• VR5000  
Positive power supply pin (3.3 V)  
• VR5000A  
Power supply pin for core (2.5 V)  
• VR5000B  
Power supply pin for core (1.8 V)  
Note  
VDDIO  
Power supply pin for I/O (3.3 V)  
Ground pin.  
GND  
Note VDDIO is only for VR5000A and VR5000B.  
Data Sheet U12031EJ3V0DS00  
 
11  
µPD30500, 30500A, 30500B  
ELECTRICAL SPECIFICATIONS  
(1) µPD30500  
Absolute Maximum Ratings  
Parameter  
Supply voltage  
Symbol  
VDD  
Condition  
Rating  
–0.5 to +4.0  
–0.5 to VDD + 0.3  
–1.5 to VDD + 0.3  
0 to +70  
Unit  
V
Note  
Input voltage  
VI  
V
Pulse of less than 10 ns  
PGA package  
V
Operating case temperature  
Storage temperature  
TC  
°C  
°C  
°C  
°C  
BGA package  
0 to +85  
Tstg  
PGA package  
–65 to +150  
–40 to +125  
BGA package  
Note The upper limit of the input voltage (VDD + 0.3) is +4.0 V.  
Cautions 1. Do not short circuit two or more outputs at the same time.  
2. The quality of the product may be degraded if the absolute maximum rating of even one of  
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,  
specify the values which if exceeded may physically damage the product. Use the product  
never exceeding these ratings.  
The specifications and conditions shown in the following DC Characteristics and AC  
Characteristics are the range within which the product can normally operate and the quality  
can be guaranteed.  
DC Characteristics (TC = 0 to +70 °C (PGA Package), TC = 0 to +85 °C (BGA Package), VDD = 3.3 V ±5 %)  
Parameter  
Symbol  
VOH  
Condition  
VDD = MIN., IOH = –4 mA  
VDD = MIN., IOL = 4 mA  
MIN.  
2.4  
MAX.  
Unit  
V
High-level output voltage  
Low-level output voltage  
VOL  
0.4  
VDD + 0.3  
+0.8  
V
Note 1  
High-level input voltage  
VIH  
2.0  
–0.5  
V
Note 1  
Low-level input voltage  
VIL  
V
Pulse of less than 10 ns  
Pulse of less than 10 ns  
–1.5  
+0.8  
V
Note 2  
Note 2  
High-level input voltage  
VIHC  
VILC  
0.8 × VDD  
–0.5  
VDD + 0.3  
0.2 × VDD  
0.2 × VDD  
2.16  
V
Low-level input voltage  
Supply current  
V
–1.5  
V
IDD  
Normal  
150 MHz  
180 MHz  
200 MHz  
A
operation  
2.54  
A
2.8  
A
Standby  
0.25  
A
Input leakage current  
ILI  
–5  
–5  
+5  
µA  
µA  
Input/output leakage current  
ILIO  
+5  
Notes 1. Not applied to the SysClock pin.  
2. Applied to the SysClock pin only.  
Remark The operating supply current is almost proportional to the operating clock frequency.  
Data Sheet U12031EJ3V0DS00  
12  
 
µPD30500, 30500A, 30500B  
Capacitance  
Parameter  
Symbol  
CIn  
Condition  
MIN.  
MAX.  
Unit  
pF  
Input capacitance  
Output capacitance  
5
7
Cout  
pF  
AC Characteristics (TC = 0 to +70 °C (PGA Package), TC = 0 to +85 °C (BGA Package), VDD = 3.3 V ±5 %)  
Clock parameter  
Parameter  
Symbol  
tCH  
Condition  
MIN.  
3.0  
3.0  
20  
MAX.  
Unit  
ns  
System clock high-level width  
System clock low-level width  
tCL  
ns  
Note 1, 2  
System clock frequency  
150 MHz  
180 MHz  
200 MHz  
150 MHz  
180 MHz  
200 MHz  
75  
90  
MHz  
MHz  
MHz  
ns  
20  
20  
100  
50  
System clock cycle  
System clock jitter  
tCP  
13.3  
11.1  
10  
50  
ns  
50  
ns  
tji  
System clock frequency > 66 MHz  
±125  
±250  
2.0  
2.0  
ps  
System clock frequency 66 MHz  
ps  
System clock rise time  
System clock fall time  
Mode clock cycle  
tCR  
ns  
tCF  
ns  
tMOC  
256 × tCP  
ns  
Notes 1. The operation of the VR5000 is guaranteed only when the PLL is operating  
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.  
Data Sheet U12031EJ3V0DS00  
13  
 
µPD30500, 30500A, 30500B  
System Interface Parameter  
Parameter  
Symbol  
Condition  
Modebit (14 : 13) = 10  
Modebit (14 : 13) = 11  
Modebit (14 : 13) = 00  
Modebit (14 : 13) = 01  
MIN.  
1.0  
MAX.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Data output hold time  
tDM  
1.1  
1.3  
1.3  
Data output delay time  
Data input setup time  
Data input hold time  
tDO  
tDS  
tDH  
5.0  
1.6  
0.5  
Boot Mode Interface Parameter  
Parameter  
More data setup time  
Mode data hold time  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
ns  
tMDS  
tMDH  
tCP × 0.35  
tCP × 0.35  
ns  
Load Coefficient  
Parameter  
Symbol  
CLD  
Condition  
MIN.  
MAX.  
1.5  
Unit  
Load coefficient  
ns/25 pF  
Data Sheet U12031EJ3V0DS00  
14  
 
µPD30500, 30500A, 30500B  
(2) µPD30500A (Preliminary)  
Absolute Maximum Ratings  
Parameter  
Symbol  
VDDIO  
VDD  
Condition  
Rating  
–0.5 to +4.0  
Unit  
V
Supply voltage  
–0.3 to +3.3  
V
Note  
Input voltage  
VI  
–0.5 to VDDIO + 0.3  
–1.5 to VDDIO + 0.3  
0 to +85  
V
Pulse of less than 10 ns  
V
Operating case temperature  
Storage temperature  
TC  
°C  
°C  
Tstg  
–40 to +125  
Note The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V.  
Cautions 1. Do not short circuit two or more outputs at the same time.  
2. The quality of the product may be degraded if the absolute maximum rating of even one of  
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,  
specify the values which if exceeded may physically damage the product. Use the product  
never exceeding these ratings.  
The specifications and conditions shown in the following DC Characteristics and AC  
Characteristics are the range within which the product can normally operate and the quality  
can be guaranteed.  
DC Characteristics (TC = 0 to +85 °C, VDDIO = 3.3 V ±5 %, VDD = 2.5 V ±5 %)  
Parameter  
Symbol  
VOH  
Condition  
VDDIO = MIN., IOH = –4 mA  
VDDIO = MIN., IOL = 4 mA  
MIN.  
2.4  
MAX.  
Unit  
V
High-level output voltage  
Low-level output voltage  
VOL  
0.4  
VDDIO + 0.3  
+0.8  
V
Note 1  
High-level input voltage  
VIH  
2.0  
V
Note 1  
Low-level input voltage  
VIL  
–0.5  
–1.5  
V
Pulse of less than 10 ns  
Pulse of less than 10 ns  
+0.8  
V
Note 2  
Note 2  
High-level input voltage  
VIHC  
VILC  
0.8 × VDDIO VDDIO + 0.3  
V
Low-level input voltage  
Input leakage current  
–0.5  
–1.5  
–5  
0.2 × VDDIO  
0.2 × VDDIO  
+5  
V
V
ILI  
µA  
µA  
Input/output leakage current  
ILIO  
–5  
+5  
Notes 1. Not applied to the SysClock pin.  
2. Applied to the SysClock pin only.  
Data Sheet U12031EJ3V0DS00  
 
15  
µPD30500, 30500A, 30500B  
Capacitance  
Parameter  
Symbol  
CIn  
Condition  
MIN.  
MAX.  
Unit  
pF  
Input capacitance  
Output capacitance  
5
7
Cout  
pF  
AC Characteristics (TC = 0 to +85 °C, VDDIO = 3.3 V ±5 %, VDD = 2.5 V ±5 %)  
Clock parameter  
Parameter  
Symbol  
tCH  
Condition  
MIN.  
3.0  
3.0  
20  
MAX.  
Unit  
ns  
System clock high-level width  
System clock low-level width  
tCL  
ns  
Note 1, 2  
System clock frequency  
100  
50  
MHz  
ns  
System clock cycle  
System clock jitter  
tCP  
tji  
10  
System clock frequency > 66 MHz  
±125  
±250  
2.0  
ps  
System clock frequency 66 MHz  
ps  
System clock rise time  
System clock fall time  
Mode clock cycle  
tCR  
ns  
tCF  
2.0  
ns  
tMOC  
256 × tCP  
ns  
Notes 1. The operation of the VR5000A is guaranteed only when the PLL is operating  
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.  
Data Sheet U12031EJ3V0DS00  
16  
 
µPD30500, 30500A, 30500B  
System Interface Parameter  
Parameter  
Symbol  
Condition  
Modebit (14 : 13) = 10  
Modebit (14 : 13) = 11  
Modebit (14 : 13) = 00  
Modebit (14 : 13) = 01  
MIN.  
1.3  
MAX.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Data output hold time  
tDM  
1.4  
1.5  
1.5  
Data output delay time  
Data input setup time  
Data input hold time  
tDO  
tDS  
tDH  
5.0  
1.6  
0.5  
Boot Mode Interface Parameter  
Parameter  
More data setup time  
Mode data hold time  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
ns  
tMDS  
tMDH  
tCP × 0.35  
tCP × 0.35  
ns  
Load Coefficient  
Parameter  
Symbol  
CLD  
Condition  
MIN.  
MAX.  
1.5  
Unit  
Load coefficient  
ns/25 pF  
Power Application Sequence  
Two kinds of power sources are provided with the VR5000A. The sequence of the power application order is not  
fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while  
the other remains off.  
Parameter  
Symbol  
Condition  
MIN.  
0
MAX.  
1
Unit  
sec  
Power application delay  
tDP  
Data Sheet U12031EJ3V0DS00  
17  
 
µPD30500, 30500A, 30500B  
(3) µPD30500B (Preliminary)  
Absolute Maximum Ratings  
Parameter  
Symbol  
VDDIO  
VDD  
Condition  
Rating  
–0.5 to +4.0  
Unit  
V
Supply voltage  
–0.3 to +2.5  
V
Note  
Input voltage  
VI  
–0.5 to VDDIO + 0.3  
–1.5 to VDDIO + 0.3  
0 to +85  
V
Pulse of less than 10 ns  
V
Operating case temperature  
Storage temperature  
TC  
°C  
°C  
Tstg  
–40 to +125  
Note The upper limit of the input voltage (VDDIO + 0.3) is +4.0 V.  
Cautions 1. Do not short circuit two or more outputs at the same time.  
2. The quality of the product may be degraded if the absolute maximum rating of even one of  
the above parameters is exceeded, even momentarily. Absolute maximum ratings, therefore,  
specify the values which if exceeded may physically damage the product. Use the product  
never exceeding these ratings.  
The specifications and conditions shown in the following DC Characteristics and AC  
Characteristics are the range within which the product can normally operate and the quality  
can be guaranteed.  
DC Characteristics (TC = 0 to +85 °C, VDDIO = 3.3 V ±5 %, VDD = 1.8 V ±0.1 V)  
Parameter  
Symbol  
VOH  
Condition  
VDDIO = MIN., IOH = –4 mA  
VDDIO = MIN., IOL = 4 mA  
MIN.  
2.4  
MAX.  
Unit  
V
High-level output voltage  
Low-level output voltage  
VOL  
0.4  
VDDIO + 0.3  
+0.8  
V
Note 1  
High-level input voltage  
VIH  
2.0  
V
Note 1  
Low-level input voltage  
VIL  
–0.5  
–1.5  
V
Pulse of less than 10 ns  
Pulse of less than 10 ns  
+0.8  
V
Note 2  
Note 2  
High-level input voltage  
VIHC  
VILC  
0.8 × VDDIO VDDIO + 0.3  
V
Low-level input voltage  
Input leakage current  
–0.5  
–1.5  
–5  
0.2 × VDDIO  
0.2 × VDDIO  
+5  
V
V
ILI  
µA  
µA  
Input/output leakage current  
ILIO  
–5  
+5  
Notes 1. Not applied to the SysClock pin.  
2. Applied to the SysClock pin only.  
Data Sheet U12031EJ3V0DS00  
 
18  
µPD30500, 30500A, 30500B  
Capacitance  
Parameter  
Symbol  
CIn  
Condition  
MIN.  
MAX.  
Unit  
pF  
Input capacitance  
Output capacitance  
5
7
Cout  
pF  
AC Characteristics (TC = 0 to +85 °C, VDDIO = 3.3 V ±5 %, VDD = 1.8 V ±0.1 V)  
Clock parameter  
Parameter  
Symbol  
tCH  
Condition  
MIN.  
3.0  
3.0  
20  
MAX.  
Unit  
ns  
System clock high-level width  
System clock low-level width  
tCL  
ns  
Note 1, 2  
System clock frequency  
100  
50  
MHz  
ns  
System clock cycle  
System clock jitter  
tCP  
tji  
10  
System clock frequency > 66 MHz  
±125  
±250  
2.0  
ps  
System clock frequency 66 MHz  
ps  
System clock rise time  
System clock fall time  
Mode clock cycle  
tCR  
ns  
tCF  
2.0  
ns  
tMOC  
256 × tCP  
ns  
Notes 1. The operation of the VR5000B is guaranteed only when the PLL is operating  
2. The operation is guaranteed if the internal operating frequency 100 MHz or higher.  
Data Sheet U12031EJ3V0DS00  
19  
 
µPD30500, 30500A, 30500B  
System Interface Parameter  
Parameter  
Symbol  
Condition  
Modebit (14 : 13) = 10  
Modebit (14 : 13) = 11  
Modebit (14 : 13) = 00  
Modebit (14 : 13) = 01  
MIN.  
1.3  
MAX.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Data output hold time  
tDM  
1.4  
1.5  
1.5  
Data output delay time  
Data input setup time  
Data input hold time  
tDO  
tDS  
tDH  
5.0  
1.6  
0.5  
Boot Mode Interface Parameter  
Parameter  
More data setup time  
Mode data hold time  
Symbol  
Condition  
MIN.  
MAX.  
Unit  
ns  
tMDS  
tMDH  
tCP × 0.35  
tCP × 0.35  
ns  
Load Coefficient  
Parameter  
Symbol  
CLD  
Condition  
MIN.  
MAX.  
1.5  
Unit  
Load coefficient  
ns/25 pF  
Power Application Sequence  
Two kinds of power sources are provided with the VR5000B. The sequence of the power application order is not  
fixed. However, make sure that either of the power supplies does not remain turned on for 1 second or more while  
the other remains off.  
Parameter  
Symbol  
Condition  
MIN.  
0
MAX.  
1
Unit  
sec  
Power application delay  
tDP  
Data Sheet U12031EJ3V0DS00  
20  
 
µPD30500, 30500A, 30500B  
Test Condition  
SysClock  
50 %  
tDO  
tDM  
All output pins  
50 %  
Test Load  
All output pins  
DUT  
C
L
= 50 pF  
Timing Chart  
Clock timing  
tCP  
tCH  
80 %  
SysClock  
50 %  
20 %  
tCL  
tCR  
tCF  
Mode clock timing  
tMOC  
ModeClock  
50 %  
Data Sheet U12031EJ3V0DS00  
 
21  
µPD30500, 30500A, 30500B  
Clock jitter  
tji  
tji  
SysClock  
50 %  
System interface edge timing  
SysClock  
tDO  
tDH  
tDM  
tDS  
SysAD (0 : 63), SysADC (0 : 7),  
SysCmd (0 : 8), SysCmdP,  
Output  
Output  
Input  
ScLine (0 : 15), ScWord (0 : 1), ScTCE, ScValid  
tDO  
tDM  
ValidOut, Release, ScCLR,  
ScCWE (0 : 1), ScDCE (0 : 1),  
ScTDE, ScTOE  
Output  
Output  
tDS  
tDH  
ValidIn, ExtRqst, RdRdy,  
WrRdy, ScDOE, ScMatch,  
Int (0 : 5), NMI  
Input  
Boot mode interface edge timing  
ModeClock  
tMDS  
tMDH  
Input  
ModeIn  
Data Sheet U12031EJ3V0DS00  
 
22  
µPD30500, 30500A, 30500B  
Clocking relations  
Cycle  
1
2
3
4
SysClock  
(input)  
PClock  
(output)  
tDO  
tDM  
SysAD Driven  
(output)  
Data  
Data  
Data  
Data  
SysAD Received  
(input)  
Data  
Data  
Data  
Data  
tDS  
tDH  
Power application sequence (VR5000A, VR5000B only)  
tDP  
tDP  
VDD 0.5VDD  
VDDIO  
0.5VDDIO  
Data Sheet U12031EJ3V0DS00  
 
23  
µPD30500, 30500A, 30500B  
Reset Timing  
Power-on reset timing  
Note 1  
VDD  
VDDI/ONote 2  
SysClock  
VDDOk  
3.135 V  
64 K SysClock  
100 ms  
256 SysClock  
ModeClock  
ModeIn  
Undefined  
tMDS  
tMDH  
bit0  
bit1  
bit255  
tDS  
ColdReset  
Reset  
64 SysClock  
tDS  
Notes 1. 3.135 V (VR5000), 2.375 V (VR5000A), 1.7 V (VR5000B)  
2. VR5000A, VR5000B only  
Cold reset timing  
H
H
VDD  
VDDIONote  
SysClock  
VDDOk  
64 K SysClock  
64 SysClock  
256 SysClock  
ModeClock  
ModeIn  
Undefined  
tMDS  
tMDH  
bit0  
bit1  
bit255  
tDS  
64 SysClock  
ColdReset  
Reset  
tDS  
Note VR5000A, VR5000B only  
Data Sheet U12031EJ3V0DS00  
 
24  
µPD30500, 30500A, 30500B  
Warm reset timing  
H
H
VDD  
VDDIONote  
SysClock  
VDDOk  
64 SysClock  
H
H
ColdReset  
Reset  
tDS  
tDS  
Note VR5000A, VR5000B only  
Data Sheet U12031EJ3V0DS00  
 
25  
µPD30500, 30500A, 30500B  
PACKAGE DRAWING  
223 PIN CERAMIC PGA  
A
< Bottom View >  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
D
8
7
6
5
4
3
2
1
T S R Q P N M L K J H G F E D C B A  
Index Mark  
J
I
F
E
K
M
L
φM  
H
G
NOTE  
ITEM MILLIMETERS  
INCHES  
1.860±0.010  
1.860±0.010  
0.080  
Each lead centerline is located within φ0.254(φ0.010 inch) of  
A
D
E
F
G
H
I
47.24±0.25  
47.24±0.25  
2.03  
its true position (T.P.) at maximum material condition.  
2.54(T.P.)  
3.30±0.2  
0.50 MIN.  
2.82  
0.100(T.P.)  
0.130±0.008  
0.019 MIN.  
0.111  
J
3.98 MAX.  
φ 1.27±0.2  
φ0.46±0.05  
0.254  
0.157 MAX.  
0.050±0.008  
φ0.018±0.002  
0.010  
K
L
M
X223RJ-100A-1  
Data Sheet U12031EJ3V0DS00  
 
26  
µPD30500, 30500A, 30500B  
272 PIN PLASTIC BGA (29x29)  
B
A
A
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
D
8
7
6
5
4
3
2
1
AA  
YWV U T R P NM L K J H G F E D C B A  
Index mark  
Z
J
Y
H
G
E
S
detail of A part  
A
A
K
S
F
φ
M
L
M
S
B *2  
φP  
M
S *3  
N
NOTES  
1. Controlling dimension  
ITEM MILLIMETERS  
INCHES  
millimeter.  
+0.008  
A
D
29.00±0.20  
1.142  
0.009  
2. Each ball centerline is located within  
its true position (T.P.) at maximum material condition.  
3. Each ball centerline is located within 0.10 mm of  
its true position (T.P.) at maximum material condition.  
φ
0.30 mm of  
+0.008  
29.00±0.20  
1.142  
0.071  
0.009  
φ
E
F
1.80  
1.27 (T.P.)  
0.050 (T.P.)  
+0.004  
0.024  
G
0.60±0.10  
0.005  
H
J
0.90  
0.035  
1.50±0.20  
0.15  
0.059±0.008  
0.006  
K
+0.006  
φ
0.030  
L
φ
0.75±0.15  
0.007  
M
N
P
Y
Z
0.30  
0.012  
0.25 MIN.  
0.10  
0.009 MIN.  
0.004  
C1.5  
0.059  
C0.5  
0.020  
S272S2-C6-2  
Data Sheet U12031EJ3V0DS00  
 
27  
µPD30500, 30500A, 30500B  
RECOMMENDED SOLDERING CONDITIONS  
Soldering this product under the following soldering conditions is recommended.  
For the details of the recommended soldering conditions, refer to Information Document Semiconductor Device  
Mounting Technology Manual (C10535E).  
For the soldering methods and recommended other than those recommended, consult NEC.  
(1) Soldering Conditions of Surface Mount Type  
µPD30500S2-150  
µPD30500S2-180  
µPD30500S2-200  
µPD30500AS2-200  
µPD30500AS2-250  
µPD30500BS2-250  
µPD30500BS2-300  
: 272-pin plastic BGA (29 × 29 mm)  
: 272-pin plastic BGA (29 × 29 mm)  
: 272-pin plastic BGA (29 × 29 mm)  
: 272-pin plastic BGA (29 × 29 mm)  
: 272-pin plastic BGA (29 × 29 mm)  
: 272-pin plastic BGA (29 × 29 mm)  
: 272-pin plastic BGA (29 × 29 mm)  
Note 1  
Note 1  
Note 1  
Note 1  
Recommended  
Soldering Method  
Infrared reflow  
Soldering Conditions  
Conditions Symbol  
Package peak temperature: 235 °C, Time: 30 sec max. (210 °C min.),  
Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is  
necessary at 125 °C for 10 hours)  
IR35-103-3  
VP15-103-3  
VPS  
Package peak temperature: 215 °C, Time: 25 to 40 sec max. (200 °C min.),  
Number of times: 3 times max., Number of days: 3Note 2 (after that, prebaking is  
necessary at 125 °C for 10 hours)  
Partial heating  
Pin temperature: 300 °C max., Time: 3 sec max. (per device side)  
Notes 1. Under development  
2. Number of days in storage after the dry pack has been opened. The storage conditions are at 25 °C, 65% RH  
MAX.  
Caution Do not use two or more soldering methods in combination (except partial heating).  
(2) Soldering Conditions of Insertion Type  
µPD30500RJ-150 : 223-pin ceramic PGA (48 × 48 mm)  
µPD30500RJ-180 : 223-pin ceramic PGA (48 × 48 mm)  
µPD30500RJ-200 : 223-pin ceramic PGA (48 × 48 mm)  
Soldering Method  
Soldering Conditions  
Wave soldering  
(Pin only)  
Solder bath temperature: 260 °C max., Time: 10 sec max.,  
Partial heating  
Pin temperature: 300 °C max., Time: 3 sec max. (Per pin)  
Caution Wave soldering is only for the lead part in order that jet solder cannot contact with the chip directly.  
Data Sheet U12031EJ3V0DS00  
28  
 
µPD30500, 30500A, 30500B  
TM  
DIFFERENCES BETWEEN THE VR5000 AND VR4310  
Item  
VR5000  
VR4310  
167 MHz MAX.  
Operating frequency  
Internal  
External  
200 MHz MAX.  
100 MHz MAX.  
83.3 MHz MAX.  
5-stage pipeline  
Pipeline  
Cache  
2-way super scalar 5-stage  
pipeline  
Primary instruction cache  
Primary data cache  
32K bytes  
32K bytes  
16K bytes  
8K bytes  
None  
Secondary cache interface Provided  
Data protection  
Byte parity  
None  
System bus  
Write data transfer rate  
9 types (DDDD/DD×DD×/  
DD××DD××/D×D×D×D×/  
DD×××DD×××/DD××××DD××××/  
D××D××D××D××/  
2 types (D/D××)  
DD××××××DD××××××/D×××D×××)  
Initialization pin at reset  
ModeIn (dedicated serial pin)  
DivMode (0:2)  
Status after last data write Access ends  
Last data retained when transfer  
rate is set  
Integer operation unit  
JTAG interface  
Corresponding instruction  
MIPS I, II, III, IV instruction sets  
MIPS I, II, III instruction sets  
Provided  
None  
None  
SyncOut-SyncIn bus  
Clock interface  
Provided  
Multiplication ratio of input 2, 3, 4, 5, 6, 7, 8  
to internal  
1.5, 2, 2.5, 3, 4, 5, 6  
Division ratio of internal to 2, 3, 4, 5, 6, 7, 8  
bus  
1.5, 2, 2.5, 3, 4, 5, 6  
TClock  
Clock output  
None  
Low-power mode  
PRId register  
Pipline does not operate.  
Pipeline/system bus operates  
at power of 1/4 of normal  
operation.  
Imp = 0×23  
Imp = 0×0B  
Data Sheet U12031EJ3V0DS00  
29  
 
µPD30500, 30500A, 30500B  
NOTES FOR CMOS DEVICES  
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS  
Note:  
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and  
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity  
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control  
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using  
insulators that easily build static electricity. Semiconductor devices must be stored and transported  
in an anti-static container, static shielding bag or conductive material. All test and measurement  
tools including work bench and floor should be grounded. The operator should be grounded using  
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need  
to be taken for PW boards with semiconductor devices on it.  
2
HANDLING OF UNUSED INPUT PINS FOR CMOS  
Note:  
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided  
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence  
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels  
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused  
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of  
being an output pin. All handling related to the unused pins must be judged device by device and  
related specifications governing the devices.  
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES  
Note:  
Power-on does not necessarily define initial status of MOS device. Production process of MOS  
does not define the initial operation status of the device. Immediately after the power source is  
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does  
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the  
reset signal is received. Reset operation must be executed immediately after power-on for devices  
having reset function.  
Note that this document is not designated as ‘preliminary’, while some of the related documents are preliminary  
versions.  
VR3000, VR4000, VR4310, VR5000, VR5000A, VR5000B, VR10000, and VR Series are trademarks of NEC Corp.  
MIPS is a trademark of MIPS Technologies Inc.  
Data Sheet U12031EJ3V0DS00  
30  
 
µPD30500, 30500A, 30500B  
Regional Information  
Some information contained in this document may vary from country to country. Before using any NEC  
product in your application, please contact the NEC office in your country to obtain a list of authorized  
representatives and distributors. They will verify:  
• Device availability  
• Ordering information  
• Product release schedule  
• Availability of related technical literature  
• Development environment specifications (for example, specifications for third-party tools and  
components, host computers, power plugs, AC supply voltages, and so forth)  
• Network requirements  
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary  
from country to country.  
NEC Electronics Inc. (U.S.)  
Santa Clara, California  
Tel: 408-588-6000  
800-366-9782  
NEC Electronics Hong Kong Ltd.  
Hong Kong  
Tel: 2886-9318  
NEC Electronics (Germany) GmbH  
Benelux Office  
Eindhoven, The Netherlands  
Tel: 040-2445845  
Fax: 2886-9022/9044  
Fax: 408-588-6130  
800-729-9288  
Fax: 040-2444580  
NEC Electronics Hong Kong Ltd.  
Seoul Branch  
Seoul, Korea  
Tel: 02-528-0303  
Fax: 02-528-4411  
NEC Electronics (France) S.A.  
Velizy-Villacoublay, France  
Tel: 01-30-67 58 00  
NEC Electronics (Germany) GmbH  
Duesseldorf, Germany  
Tel: 0211-65 03 02  
Fax: 01-30-67 58 99  
Fax: 0211-65 03 490  
NEC Electronics Singapore Pte. Ltd.  
United Square, Singapore 1130  
Tel: 65-253-8311  
NEC Electronics (France) S.A.  
Spain Office  
Madrid, Spain  
NEC Electronics (UK) Ltd.  
Milton Keynes, UK  
Tel: 01908-691-133  
Fax: 65-250-3583  
Tel: 91-504-2787  
Fax: 01908-670-290  
Fax: 91-504-2860  
NEC Electronics Taiwan Ltd.  
Taipei, Taiwan  
Tel: 02-2719-2377  
NEC Electronics Italiana s.r.l.  
Milano, Italy  
NEC Electronics (Germany) GmbH  
Scandinavia Office  
Tel: 02-66 75 41  
Fax: 02-2719-5951  
Taeby, Sweden  
Fax: 02-66 75 42 99  
Tel: 08-63 80 820  
NEC do Brasil S.A.  
Fax: 08-63 80 388  
Electron Devices Division  
Rodovia Presidente Dutra, Km 214  
07210-902-Guarulhos-SP Brasil  
Tel: 55-11-6465-6810  
Fax: 55-11-6465-6829  
J99.1  
Data Sheet U12031EJ3V0DS00  
31  
 
µPD30500, 30500A, 30500B  
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some  
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
No part of this document may be copied or reproduced in any form or by any means without the prior written  
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in  
this document.  
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual  
property rights of third parties by or arising from use of a device described herein or any other liability arising  
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights  
or other intellectual property rights of NEC Corporation or others.  
Descriptions of circuits, software, and other related information in this document are provided for illustrative  
purposes in semiconductor product operation and application examples. The incorporation of these circuits,  
software, and information in the design of the customer's equipment shall be done under the full responsibility  
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third  
parties arising from the use of these circuits, software, and information.  
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,  
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or  
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety  
measures in its design, such as redundancy, fire-containment, and anti-failure features.  
NEC devices are classified into the following three quality grades:  
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a  
customer designated “quality assurance program“ for a specific application. The recommended applications of  
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device  
before using it in a particular application.  
Standard: Computers, office equipment, communications equipment, test and measurement equipment,  
audio and visual equipment, home electronic appliances, machine tools, personal electronic  
equipment and industrial robots  
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster  
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed  
for life support)  
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life  
support systems or medical equipment for life support, etc.  
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.  
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,  
they should contact an NEC sales representative in advance.  
M7 98.8  
 

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