Philips Stereo Amplifier TDA8586 User Manual

INTEGRATED CIRCUITS  
DATA SHEET  
TDA8586  
Power amplifier with load detection  
and auto BTL/SE selection  
Preliminary specification  
2001 Jul 23  
Supersedes data of 1999 Apr 08  
File under Integrated Circuits, IC01  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
QUICK REFERENCE DATA  
SYMBOL  
VP  
Iq(tot)  
Istb  
PARAMETER  
CONDITIONS  
MIN.  
8.0  
TYP.  
MAX.  
18  
UNIT  
operating supply voltage  
total quiescent current  
standby supply current  
voltage gain  
V
VP = 14.4 V, SE mode  
VP = 14.4 V  
25  
31  
140  
1
170  
100  
27  
mA  
µA  
dB  
dB  
Gv  
SE mode  
26  
32  
BTL mode  
33  
Bridge-tied load application  
Po  
output power  
VP = 14.4 V; RL = 4 Ω  
THD = 0.5%  
14  
17  
15  
W
W
%
THD = 10%  
21  
THD  
VOO  
total harmonic distortion  
DC output offset voltage  
fi = 1 kHz; Po = 1 W;  
VP = 14.4 V; RL = 4 Ω  
VP = 14.4 V; RL = 4 ;  
mute condition  
0.05  
0.15  
10  
20  
mV  
VP = 14.4 V; on condition  
0
100  
200  
mV  
Vn(o)  
noise output voltage  
Rs = 1 kΩ; VP = 14.4 V  
100  
µV  
Single-ended application  
Po  
output power  
VP = 14.4 V; RL = 4 Ω  
THD = 0.5%  
4
5
4.5  
6
W
W
%
THD = 10%  
THD  
VOO  
total harmonic distortion  
DC output offset voltage  
fi = 1 kHz; Po = 1 W;  
VP = 14.4 V; RL = 4 Ω  
VP = 14.4 V; RL = 4 ;  
mute condition  
0.08  
0.15  
10  
20  
mV  
VP = 14.4 V; on condition  
0
100  
150  
mV  
Vn(o)  
noise output voltage  
Rs = 1 kΩ; VP = 14.4 V  
80  
µV  
2001 Jul 23  
3
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
BLOCK DIAGRAM  
V
V
P1  
P2  
16  
2
5
IN1  
60  
V/I  
k  
OA  
1
+
OUT1  
+
+
V/I  
60  
kΩ  
TDA8586Q  
OA  
3
4
V
Pn  
HVP1  
OUT2  
+
+
OA  
6
IN2  
+
60  
V/I  
kΩ  
7
IN3  
60  
V/I  
kΩ  
OA  
17  
+
OUT3  
HVP2  
+
11  
ACREF  
+
V/I  
V
Pn  
60  
kΩ  
OA  
15  
14  
V
Pn  
30 kΩ  
+
BUFFER  
+
OA  
8
IN4  
OUT4  
DIAG  
+
V/I  
60  
kΩ  
13  
12  
MSO  
INTERFACE  
DIAGNOSTIC  
9
10  
MGR023  
PGND2  
PGND1  
Fig.1 Block diagram SOT243-1.  
4
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
V
V
P1  
P2  
13  
18  
2
IN1  
60  
V/I  
kΩ  
OA  
17  
+
OUT1  
+
+
V/I  
60  
kΩ  
TDA8586TH  
OA  
1
19  
20  
V
Pn  
n.c.  
HVP1  
OUT2  
+
+
OA  
3
IN2  
+
60  
V/I  
kΩ  
4
IN3  
60  
V/I  
kΩ  
OA  
14  
+
OUT3  
HVP2  
+
6
ACREF  
+
V/I  
V
Pn  
60  
kΩ  
OA  
12  
11  
V
Pn  
30 kΩ  
+
BUFFER  
+
OA  
5
8
IN4  
OUT4  
DIAG  
+
V/I  
60  
kΩ  
7
MSO  
INTERFACE  
10  
DIAGNOSTIC  
9
15  
PGND2  
16  
MGR024  
DDDSEL OVERRULE  
PGND1  
Fig.2 Block diagram SOT418-2 (HSOP20 heatsink up).  
5
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
PINNING  
PIN  
SYMBOL  
DESCRIPTION  
TDA8586Q  
TDA8586TH  
n.c.  
5
1
2
not connected  
IN1  
non-inverting input 1  
inverting input 2  
IN2  
6
3
IN3  
7
4
non inverting input 3  
inverting input 4  
IN4  
8
5
ACREF  
DIAG  
MSO  
11  
12  
13  
6
common signal input  
diagnostic output/mode fix  
7
8
mode select mute, standby or on  
mode selection overrule  
OVERRULE  
DDDSEL  
OUT4  
HVP2  
VP2  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
2 or 10% dynamic distortion detection  
SE output 4 (negative)  
14  
15  
16  
17  
10  
9
buffer output/BTL output 2 (negative)  
supply voltage 2  
OUT3  
PGND2  
PGND1  
OUT1  
VP1  
SE output 3/BTL output 2 (positive)  
power ground 2  
power ground 1  
1
SE output 1/BTL output 1 (positive)  
supply voltage 1  
2
HVP1  
OUT2  
3
buffer output/BTL output 1 (negative)  
SE output 2 (negative)  
4
2001 Jul 23  
6
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
handbook, halfpage  
OUT1  
1
2
V
P1  
HVP1  
OUT2  
IN1  
3
handbook, halfpage  
OUT2 20  
HVP1 19  
1
2
n.c.  
4
IN1  
5
V
18  
17  
16  
15  
14  
13  
12  
11  
3
IN2  
6
IN2  
P1  
OUT1  
PGND1  
PGND2  
OUT3  
4
IN3  
7
IN3  
5
IN4  
8
IN4  
TDA8586TH  
6
ACREF  
DIAG  
MSO  
9
PGND1  
PGND2  
ACREF  
DIAG  
MSO  
TDA8586Q  
7
10  
11  
12  
13  
14  
15  
16  
17  
V
8
P2  
HVP2  
OUT4  
9
OVERRULE  
DDDSEL  
10  
MGR026  
OUT4  
HVP2  
V
P2  
OUT3  
MGR025  
Fig.3 Pin configuration (SOT243-1).  
Fig.4 Pin configuration (SOT418-2).  
2001 Jul 23  
7
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
FUNCTIONAL DESCRIPTION  
The presence of the load is measured after the transition  
between standby and mute. The IC will determine if there  
is an acceptable load on both outputs (OUT2 and OUT4).  
If both outputs are unloaded, the IC will switch to a  
2 speaker mode of operation (BTL mode), unless it is  
overruled.  
The TDA8586 is a multi-purpose power amplifier with four  
amplifiers and 2 buffer stages, which can be connected in  
the following configurations with high output power and  
low distortion:  
Dual Bridge-Tied Load (BTL) amplifiers  
There are two options to overrule:  
Quad Single-Ended (SE) amplifiers.  
1. Before transition from mute to on, after a load  
detection, pulling the diagnostic output above 9.5 V  
will force the IC into 4 speaker mode  
In the BTL mode of operation, the 2 buffer amplifiers act as  
inverting amplifiers to complete the bridge across the front  
amplifiers (OUT1 and OUT3) and the rear outputs (OUT2  
and OUT4) enter a high-impedance state.  
2. TDA8586TH: pulling the OVERRULE pin according  
pinning table.  
In the SE mode of operation, the buffers act as an AC  
ground path thereby eliminating the need for series  
capacitors on the speaker outputs.  
Care should be taken with the OVERRULE function as it  
works during the on mode. If there is a 2 or 4 speaker  
mode change during the on mode a large plop can be  
heard on the speakers.  
Diagnostics:  
While the IC is in the mute mode, the diagnostic output  
will signal the mode of operation when the IC is not  
overruled  
The ACREF input (common signal input) acts with the four  
signal inputs (IN1 to IN4) to provide quasi differential  
inputs. A capacitor must be connected to this pin of which  
the ground pin should be connected to the ground at the  
signal source (usually the ground at the audio signal  
processor). This capacitor has a dual function. During the  
speaker detection, the signal ground capacitor is used to  
set the time constant of the measurement (and thus  
determines the minimum required switch-on time).  
The capacitor on the MSO pin allows the integrate function  
to provide immunity to outside noises during load  
detection.  
In the on mode the diagnostic output will signal any fault  
in the IC or if the output of any amplifier is clipping with  
a distortion of 10% (or 2% depending on selected  
clip-mode).  
Special attention is given to the dynamic behaviour as  
follows:  
Noise suppression during engine start  
No plops when switching from standby to on  
Slow offset change between mute and on (controlled by  
MSO pin)  
Low noise levels, which are independent of the supply  
voltage.  
Protections are included to avoid the IC being damaged at:  
Over temperature: Tj > 150 °C  
Short-circuit of the output pin(s) to ground or supply rail.  
When short-circuited, the power dissipation is limited  
ESD protection (Human Body Model 3000 V and  
Machine Model 300 V).  
2001 Jul 23  
8
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
mute  
mute  
on  
on  
on  
state  
standby  
condition  
load detect  
no load detect  
no clipping/shorts  
clipping  
short-circuit  
V
P
0
V
P
minimum 1 s  
SE detection  
9 V  
MSO  
3 V  
0
BTL detection  
BTL detected  
SE detected  
5 V  
diagnostic  
information  
0
10 V  
The mode is overruled only from  
BTL to SE when the diagnostic pin  
is excited with a pulse of 10 V.  
diagnostic  
overrule  
0
5 V  
This voltage must remain present.  
Whatever the load detection has found the mode of operation will be inverted.  
Toggling between the 2 modes is possible.  
mode select  
0
short-circuit to supply  
short-circuit over load  
short-circuit to ground  
amplifier  
output  
0.5V  
P
0
short-circuit to supply  
short-circuit over load  
0.5V  
buffer/amplifier  
output  
P
0
short-circuit to ground  
MGR027  
Fig.5 Timing diagram including diagnostics.  
9
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL  
VP  
PARAMETER  
CONDITIONS  
operating  
MIN.  
MAX.  
18  
UNIT  
supply voltage  
8
V
V
load dump protected;  
see Fig.6  
45  
VDIAG  
IOSM  
IORM  
Vrp  
voltage on diagnostic pin  
18  
6
V
A
A
V
V
non-repetitive peak output current  
repetitive peak output current  
reverse polarity voltage  
4
note 1  
6
Vsc  
AC and DC short-circuit voltage of output pins  
across loads and to ground or supply pins  
18  
Ptot  
Tj  
total power dissipation  
junction temperature  
55  
75  
W
150  
+150  
+150  
°C  
°C  
°C  
Tstg  
Tamb  
storage temperature  
operating ambient temperature  
40  
Note  
1. A large reverse current will flow, therefore external protection is needed (fuse and reverse diode).  
MGL404  
handbook, halfpage  
45 V  
V
P
14.4 V  
t (ms)  
t
t
f
r
Fig.6 Load dump voltage waveform.  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
in free air  
VALUE  
UNIT  
Rth(j-a)  
Rth(j-c)  
thermal resistance from junction to ambient  
thermal resistance from junction to case  
40  
2
K/W  
K/W  
2001 Jul 23  
10  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
CHARACTERISTICS  
VP = 14.4 V; Tamb = 25 °C; fi = 1 kHz; RL = ; measured in test circuit of Fig.8; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
VP  
operating supply voltage  
total quiescent current  
standby current  
8.0  
14.4  
18  
V
Iq(tot)  
Istb  
SE mode  
6.0  
140  
1
170  
100  
mA  
µA  
V
VO  
DC output voltage  
VP = 14.4 V  
7.0  
7.0  
VP(mute)  
Vo  
low supply voltage mute  
8.0  
V
single-ended and bridge-tied  
load output voltage  
VP = 14.4 V; RL = 4 Ω  
mute condition  
on condition  
20  
100  
mV  
mV  
V
VI  
DC input voltage  
VP = 14.4 V  
4.0  
PIN MSO  
VMSO  
voltage at pin MSO  
standby condition  
0
3.0  
0.8  
4
V
mute condition; note 1  
on condition  
2.0  
8.0  
V
10.5  
40  
V
IMSO  
input current  
mute pin at standby condition;  
V
5
µA  
MSO < 0.8 V  
Diagnostic; output buffer (open-collector); see Figs 7 to 8  
VDIAG(L) diagnostic output voltage LOW Isink = 1 mA  
ILI  
0.3  
0.8  
1
V
leakage current  
VDIAG = 14.4 V  
µA  
V
VDIAG(or)  
diagnostic override voltage  
in mute mode after load  
detection  
10.5  
18  
VDIAG(4ch)  
CD2  
diagnostic 4 channel indication mute, after load detection with  
0.3  
2
0.8  
3.5  
13  
V
voltage  
4 speakers connected  
clip detector LOW  
THD mode; VDIAG > 3 V;  
0.5  
7
%
%
R = 10 kΩ  
CD10  
clip detector HIGH  
THD mode (default);  
10  
V
DIAG > 3 V; R = 10 kΩ  
CLIP DETECT CONTROL PIN  
VDDDSEL  
voltage at DDD select pin to  
obtain:  
10% DDD  
0
1
V
2% DDD  
3
6
V
IDDDSEL  
Input current DDD select pin  
VDDDSEL = 5 V  
15  
140  
µA  
Stereo BTL application (see Fig.7)  
THD  
total harmonic distortion  
fi = 1 kHz; Po = 1 W; RL = 4 Ω  
45 Hz < fi < 10 kHz; Po = 1 W;  
RL = 4 ; filter: f < 30 kHz  
0.05  
0.3  
0.15  
%
%
Po  
output power  
VP = 14.4 V; RL = 4 ; note 2  
THD = 0.5%  
14  
17  
15  
21  
W
W
THD = 10%  
2001 Jul 23  
11  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
SYMBOL  
Gv  
PARAMETER  
voltage gain  
CONDITIONS  
Vi(rms) = 15 mV  
MIN.  
31  
TYP.  
32  
MAX.  
33  
UNIT  
dB  
Gv  
αcs  
channel unbalance  
channel separation  
DC output offset voltage  
Vi(rms) = 15 mV  
0.7  
45  
0
+0.7  
100  
20  
dB  
Po = 2 W; fi = 1 kHz; RL = 4 Ω  
VP = 14.4 V; on condition  
55  
0
dB  
VOO  
mV  
mV  
VP = 14.4 V; RL = 4 ;  
mute condition  
10  
Vn(o)  
noise output voltage on  
noise output voltage mute  
output voltage mute  
Rs = 1 k; VP = 14.4 V; note 3  
note 3  
100  
0
150  
20  
µV  
µV  
µV  
Vn(o)(mute)  
Vo(mute)  
SVRR  
Vi(rms) = 1 V  
3
500  
supply voltage ripple rejection: Rs = 0 ; fi = 1 kHz;  
V
ripple = 2 V (p-p)  
on condition  
45  
55  
40  
55  
70  
60  
dB  
dB  
kΩ  
mute condition  
Zi  
input impedance  
input referenced to ground  
90  
Quad SE application (see Fig.8)  
THD  
total harmonic distortion  
fi = 1 kHz; Po = 1 W; RL = 4 Ω  
45 Hz < fi < 10 kHz; Po = 1 W;  
RL = 4 ; filter: f < 30 kHz  
0.05  
0.5  
0.15  
%
%
Po  
output power  
VP = 14.4 V; RL = 4 ; note 2  
THD = 0.5%  
4
4.5  
6
W
THD = 10%  
5
W
Gv  
voltage gain  
Vi(rms) = 15 mV  
25  
0.7  
40  
26  
0
27  
+0.7  
100  
20  
dB  
dB  
dB  
mV  
mV  
Gv  
αcs  
channel unbalance  
channel separation  
DC output offset voltage  
Vi(rms) = 15 mV  
Po = 2 W; fi = 1 kHz; RL = 4 Ω  
VP = 14.4 V; on condition  
50  
0
VOO  
VP = 14.4 V; RL = 4 ;  
mute condition  
10  
Vn(o)  
noise output voltage on  
noise output voltage mute  
output voltage mute  
Rs = 1 k; VP = 14.4 V; note 3  
note 3  
80  
0
150  
20  
µV  
µV  
µV  
Vn(o)(mute)  
Vo(mute)  
SVRR  
Vi(rms) = 1 V  
3
500  
supply voltage ripple rejection Rs = 0 ; fi = 1 kHz;  
Vripple = 2 V (p-p)  
on condition  
43  
55  
47  
70  
dB  
dB  
mute condition  
Notes  
1. Tolerances on the mute level is tight because of the usage of this pin for integration during load detection.  
2. The output power is measured directly on the pins of the IC.  
3. The noise output is measured in a bandwidth of 20 Hz to 20 kHz.  
2001 Jul 23  
12  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
APPLICATION INFORMATION  
V
P
1000 µF  
(16/40 V)  
100  
nF  
V
V
P1  
P2  
16  
2
220 nF  
IN1  
5
60  
V/I  
V
front  
OA  
INL  
kΩ  
OUT1  
1
+
+
+
4 or 8 Ω  
+
V/I  
60  
kΩ  
TDA8586Q  
OA  
HVP1  
OUT2  
3
4
V
Pn  
+
+
OA  
220 nF  
220 nF  
IN2  
IN3  
6
7
+
V/I  
60  
kΩ  
60  
V
front  
V/I  
OA  
INR  
kΩ  
OUT3  
HVP2  
17  
15  
+
+
ACREF 11  
47 µF  
+
4 or 8 Ω  
(10 V)  
+
V/I  
V
Pn  
60  
kΩ  
OA  
V
Pn  
30 kΩ  
+
BUFFER  
+
OA  
220 nF  
IN4  
8
14 OUT4  
+
V/I  
60  
kΩ  
switched  
+9 V  
+5 V  
10 kΩ  
30 kΩ  
MSO  
13  
12 DIAG  
INTERFACE  
DIAGNOSTIC  
15 kΩ  
10  
PGND2  
9
4.7 µF  
(10 V)  
MGR028  
PGND1  
switch  
Fig.7 Stereo bridge-tied load application (SOT243-1).  
13  
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
V
P
1000 µF  
(16/40 V)  
100  
nF  
V
V
P1  
P2  
16  
2
220 nF  
IN1  
5
60  
V/I  
V
front  
OA  
INL  
kΩ  
OUT1  
1
+
+
+
4 or 8 Ω  
+
V/I  
60  
kΩ  
TDA8586Q  
OA  
HVP1  
OUT2  
3
4
V
Pn  
+
+
4 or 8 Ω  
+
OA  
220 nF  
220 nF  
IN2  
IN3  
6
7
+
V/I  
60  
kΩ  
V
rear  
INL  
60  
V
front  
V/I  
OA  
INR  
kΩ  
OUT3  
17  
+
+
ACREF 11  
47 µF  
+
4 or 8 Ω  
(10 V)  
+
V/I  
V
Pn  
60  
kΩ  
OA  
HVP2  
OUT4  
15  
14  
V
Pn  
30 kΩ  
+
+
4 or 8 Ω  
BUFFER  
+
OA  
220 nF  
IN4  
8
+
V/I  
60  
kΩ  
V
rear  
INR  
+5 V  
switched  
+9 V  
10 kΩ  
30 kΩ  
MSO  
13  
12 DIAG  
INTERFACE  
DIAGNOSTIC  
10  
PGND2  
9
15 kΩ  
MGR029  
PGND1  
4.7 µF  
(10 V)  
switch  
Fig.8 Quad single-ended application (SOT243-1).  
14  
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
V
P
1000 µF  
(16/40 V)  
100  
nF  
V
V
P1  
18  
P2  
13  
220 nF  
IN1  
2
60  
V/I  
V
front  
OA  
INL  
kΩ  
OUT1  
HVP1  
17  
19  
+
+
+
4 or 8 Ω  
+
V/I  
60  
kΩ  
TDA8586TH  
OA  
1
3
n.c.  
IN2  
V
Pn  
+
+
OA  
220 nF  
220 nF  
20 OUT2  
+
V/I  
60  
kΩ  
IN3  
4
6
V/I  
60  
kΩ  
V
front  
OA  
INR  
OUT3  
HVP2  
14  
12  
+
+
ACREF  
+
47 µF  
(10 V)  
4 or 8 Ω  
+
V/I  
V
Pn  
60  
kΩ  
OA  
V
Pn  
30 kΩ  
+
BUFFER  
+
OA  
220 nF  
IN4  
5
8
11 OUT4  
+
V/I  
60  
kΩ  
switched  
+9 V  
+5 V  
10 kΩ  
30 kΩ  
DIAG  
7
MSO  
INTERFACE  
DIAGNOSTIC  
15 kΩ  
10  
9
15  
PGND2  
16  
4.7 µF  
(10 V)  
DDDSEL  
OVERRULE  
PGND1  
switch  
MGR030  
Fig.9 Stereo bridge-tied load application (SOT418-2).  
15  
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
V
P
1000 µF  
(16/40 V)  
100  
nF  
V
V
P1  
18  
P2  
13  
220 nF  
IN1  
2
60  
V/I  
V
front  
OA  
INL  
kΩ  
OUT1  
17  
+
+
+
4 or 8 Ω  
+
V/I  
60  
kΩ  
TDA8586TH  
OA  
HVP1  
OUT2  
n.c.  
IN2  
1
3
19  
20  
V
Pn  
+
+
4 or 8 Ω  
+
OA  
220 nF  
220 nF  
+
V/I  
60  
kΩ  
V
rear  
INL  
IN3  
4
6
60  
V
front  
V/I  
OA  
INR  
kΩ  
OUT3  
14  
12  
+
+
ACREF  
+
47 µF  
(10 V)  
4 or 8 Ω  
+
V/I  
V
Pn  
60  
kΩ  
OA  
HVP2  
OUT4  
V
Pn  
30 kΩ  
+
+
4 or 8 Ω  
BUFFER  
+
OA  
220 nF  
IN4  
5
8
11  
+
V/I  
60  
kΩ  
V
rear  
INR  
+5 V  
switched  
+9 V  
10 kΩ  
DIAG  
30 kΩ  
MSO  
7
INTERFACE  
DIAGNOSTIC  
10  
9
15  
PGND2  
16  
15 kΩ  
MGR031  
DDDSEL  
OVERRULE  
PGND1  
4.7 µF  
(10 V)  
switch  
Fig.10 Quad single-ended application (SOT418-2).  
16  
2001 Jul 23  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
INTERNAL PIN CONFIGURATION  
PIN  
TDA8586TH  
NAME  
EQUIVALENT CIRCUIT  
2, 3, 4, 5 and 6  
inputs  
V
P
handbook, halfpage  
IN  
MGE014  
11, 12, 14, 17,  
19 and 20  
outputs  
handbook, halfpage  
V
P
OUT  
0.5 V  
MGE015  
P
8
mode select  
V
P
handbook, halfpage  
MGE016  
2001 Jul 23  
17  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
PACKAGE OUTLINES  
DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)  
SOT243-1  
non-concave  
D
h
x
D
E
h
view B: mounting base side  
d
A
2
B
j
E
A
L
3
L
Q
c
2
v
M
1
17  
e
e
m
w
M
1
Z
b
p
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
(1)  
(1)  
UNIT  
A
A
b
c
D
d
D
E
e
e
e
E
j
L
L
3
m
Q
v
w
x
Z
2
p
h
1
2
h
17.0 4.6 0.75 0.48 24.0 20.0  
15.5 4.4 0.60 0.38 23.6 19.6  
12.2  
11.8  
3.4 12.4 2.4  
3.1 11.0 1.6  
2.00  
1.45  
2.1  
1.8  
6
mm  
10  
2.54 1.27 5.08  
0.8  
4.3  
0.4 0.03  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
97-12-16  
99-12-17  
SOT243-1  
2001 Jul 23  
18  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
HSOP20: plastic, heatsink small outline package; 20 leads; low stand-off height  
SOT418-2  
E
A
D
x
X
c
E
H
y
2
v
M
A
E
D
1
D
2
10  
1
pin 1 index  
Q
A
A
2
(A )  
3
E
1
A
4
θ
L
p
detail X  
20  
11  
w M  
Z
b
p
e
0
5
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
max.  
(1)  
(2)  
(2)  
A
A
A
b
c
D
D
D
E
E
1
E
e
H
L
p
Q
v
w
x
y
Z
θ
UNIT  
2
3
4
p
1
2
2
E
8°  
0°  
+0.12 0.53 0.32  
0.02 0.40 0.23  
16.0 13.0 1.1 11.1 6.2  
15.8 12.6 0.9 10.9 5.8  
2.9  
2.5  
14.5 1.1  
13.9 0.8  
1.7  
1.5  
2.5  
2.0  
3.5  
3.2  
mm  
1.27  
3.5  
0.35  
0.25 0.25 0.03 0.07  
Notes  
1. Limits per individual lead.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
98-02-25  
99-11-12  
SOT418-2  
2001 Jul 23  
19  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
SOLDERING  
Introduction  
Typical reflow peak temperatures range from  
215 to 250 °C. The top-surface temperature of the  
packages should preferable be kept below 220 °C for  
thick/large packages, and below 235 °C for small/thin  
packages.  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
WAVE SOLDERING  
There is no soldering method that is ideal for all IC  
packages. Wave soldering is often preferred when  
through-hole and surface mount components are mixed on  
one printed-circuit board. Wave soldering can still be used  
for certain surface mount ICs, but it is not suitable for fine  
pitch SMDs. In these situations reflow soldering is  
recommended.  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
To overcome these problems the double-wave soldering  
method was specifically developed.  
If wave soldering is used the following conditions must be  
observed for optimal results:  
Through-hole mount packages  
Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
SOLDERING BY DIPPING OR BY SOLDER WAVE  
The maximum permissible temperature of the solder is  
260 °C; solder at this temperature must not be in contact  
with the joints for more than 5 seconds. The total contact  
time of successive solder waves must not exceed  
5 seconds.  
For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
The device may be mounted up to the seating plane, but  
the temperature of the plastic body must not exceed the  
specified maximum storage temperature (Tstg(max)). If the  
printed-circuit board has been pre-heated, forced cooling  
may be necessary immediately after soldering to keep the  
temperature within the permissible limit.  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
The footprint must incorporate solder thieves at the  
downstream end.  
For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
MANUAL SOLDERING  
Apply the soldering iron (24 V or less) to the lead(s) of the  
package, either below the seating plane or not more than  
2 mm above it. If the temperature of the soldering iron bit  
is less than 300 °C it may remain in contact for up to  
10 seconds. If the bit temperature is between  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
300 and 400 °C, contact may be up to 5 seconds.  
Surface mount packages  
Typical dwell time is 4 seconds at 250 °C.  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
REFLOW SOLDERING  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
MANUAL SOLDERING  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C. When using a dedicated tool, all other leads can  
be soldered in one operation within 2 to 5 seconds  
between 270 and 320 °C.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
2001 Jul 23  
20  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
Suitability of IC packages for wave, reflow and dipping soldering methods  
SOLDERING METHOD  
WAVE  
REFLOW(1) DIPPING  
suitable(2)  
MOUNTING  
PACKAGE  
Through-hole mount DBS, DIP, HDIP, SDIP, SIL  
suitable  
Surface mount  
BGA, HBGA, LFBGA, SQFP, TFBGA  
not suitable  
not suitable(3)  
suitable  
suitable  
HBCC, HLQFP, HSQFP, HSOP, HTQFP,  
HTSSOP, HVQFN, SMS  
PLCC(4), SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO  
suitable  
suitable  
not recommended(4)(5) suitable  
not recommended(6)  
suitable  
Notes  
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.  
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink  
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).  
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;  
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is  
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
2001 Jul 23  
21  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
DATA SHEET STATUS  
PRODUCT  
DATA SHEET STATUS(1)  
STATUS(2)  
DEFINITIONS  
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
Preliminary data  
Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change  
Notification (CPCN) procedure SNW-SQ-650A.  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes, without notice, in the  
products, including circuits, standard cells, and/or  
software, described or contained herein in order to  
improve design and/or performance. Philips  
Semiconductors assumes no responsibility or liability for  
the use of any of these products, conveys no licence or title  
under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that  
these products are free from patent, copyright, or mask  
work right infringement, unless otherwise specified.  
Application information  
Applications that are  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2001 Jul 23  
22  
 
Philips Semiconductors  
Preliminary specification  
Power amplifier with load detection and  
auto BTL/SE selection  
TDA8586  
NOTES  
2001 Jul 23  
23  
 
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72  
SCA  
© Philips Electronics N.V. 2001  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
753503/03/pp24  
Date of release: 2001 Jul 23  
Document order number: 9397 750 08407  
 

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