Renesas Power Supply HD74HCT1G04 User Guide

HD74HCT1G04  
Inverter  
REJ03D0193–0500Z  
(Previous ADE-205-303C (Z))  
Rev.5.00  
Jan.28.2004  
Description  
The HD74HCT1G04 is high-speed CMOS inverter using silicon gate CMOS process. With CMOS low  
power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages  
construction with buffer provides wide noise margin and stable output.  
Features  
The basic gate function is lined up as Renesas uni logic series.  
Supplied on emboss taping for high-speed automatic mounting.  
TTL compatible input level.  
Supply voltage range : 4.5 to 5.5 V  
Operating temperature range : –40 to +85°C  
|IOH| = IOL = 2 mA (min)  
Ordering Information  
Part Name  
Package Type  
Package Code  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
HD74HCT1G04CME CMPAK-5 pin  
CMPAK-5V  
CM  
E (3,000 pcs/reel)  
Rev.5.00, Jan.28.2004, page 1 of 7  
 
HD74HCT1G04  
Absolute Maximum Ratings  
Item  
Symbol  
VCC  
VI  
Ratings  
–0.5 to 7.0  
–0.5 to VCC + 0.5  
–0.5 to VCC + 0.5  
±20  
Unit Test Conditions  
Supply voltage range  
Input voltage range *1  
Output voltage range *1, 2  
Input clamp current  
Output clamp current  
V
V
VO  
V
Output : H or L  
VI < 0 or VI > VCC  
VO < 0 or VO >VCC  
VO = 0 to VCC  
IIK  
mA  
mA  
mA  
mA  
IOK  
±20  
Continuous output current IO  
±25  
Continuous current through ICC or IGND  
VCC or GND  
±25  
Maximum power dissipation PT  
at Ta = 25°C (in still air) *3  
200  
mW  
Storage temperature  
Notes:  
Tstg  
–65 to 150  
°C  
The absolute maximum ratings are values, which must not individually be exceeded, and  
furthermore, no two of which may be realized at the same time.  
1. The input and output voltage ratings may be exceeded if the input and output clamp-current  
ratings are observed.  
2. This value is limited to 5.5 V maximum.  
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.  
Recommended Operating Conditions  
Item  
Symbol  
VCC  
VI  
Min  
4.5  
0
Max  
5.5  
5.5  
VCC  
2
Unit  
V
Test Conditions  
Supply voltage range  
Input voltage range  
Output voltage range  
Output current  
V
VO  
0
V
IOL  
0
mA  
VCC = 4.5 to 5.5 V  
VCC = 4.5 to 5.5 V  
VCC = 4.5 to 5.5 V  
IOH  
–2  
Input rise / fall time  
(0.3 V to 2.7 V)  
tr, tf  
500  
ns  
°C  
Operating temperature  
Ta  
–40  
85  
Note: Unused or floating inputs must be held high or low.  
Rev.5.00, Jan.28.2004, page 3 of 7  
 
HD74HCT1G04  
Electrical Characteristics  
VCC  
Ta = 25°C  
Min Typ  
Ta = –40 to 85°C  
Item  
Symbol (V)  
Unit Test Conditions  
Max Min  
Max  
Input voltage  
VIH  
4.5 to 2.0  
5.5  
2.0  
V
VIL  
4.5 to —  
5.5  
0.8  
0.8  
Output voltage VOH  
VOL  
4.5  
4.5  
4.5  
4.5  
5.5  
5.5  
4.4  
4.5  
4.4  
4.13  
V
VIN = VIL IOH = –20 µA  
4.18 4.31  
IOH = –2 mA  
IN = VIH IOL = 20 µA  
IOL = 2 mA  
0.0  
0.1  
0.1  
V
0.17 0.26  
0.33  
±1.0  
10.0  
Input current  
IIN  
±0.1  
1.0  
µA VIN = VCC or GND  
Operating  
current  
ICC  
µA VIN = VCC or GND  
Quiescent  
supply current  
ICCT  
5.5  
2.0  
2.9  
mA One input VIN = 2.4 V,  
other input VCC or GND  
Rev.5.00, Jan.28.2004, page 4 of 7  
 
HD74HCT1G04  
Switching Characteristics  
Ta = 25°C  
Min  
Item  
Symbol  
Unit  
Test Conditions  
Typ  
Max  
Output rise / fall time  
tTLH  
tTHL  
6
10  
ns  
Test circuit  
Propagation delay time tPLH  
tPHL  
7.5  
10  
12  
17  
ns  
Test circuit  
(CL = 15 pF, tr = tf = 6 ns, VCC = 5 V)  
VCC Ta = 25°C  
Symbol (V)  
Ta = –40 to 85°C  
Item  
Unit Test Conditions  
Min Typ Max Min  
Max  
Output rise / fall time  
tTLH  
tTHL  
4.5  
14  
25  
31  
ns Test circuit  
Propagation delay time tPLH  
tPHL  
4.5  
4.5  
11.2 16  
16.4 27  
20  
31  
5
ns Test circuit  
Input capacitance  
CIN  
2.5  
10  
5
pF  
pF  
Equivalent capacitance CPD  
(CL = 50 pF, tr = tf = 6 ns)  
Note:  
CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see  
test circuit). The average operating current without load is calculated according to the expression  
below.  
ICC (opr) = CPD VCC fIN + ICC  
Rev.5.00, Jan.28.2004, page 5 of 7  
 
HD74HCT1G04  
Test Circuit  
VCC  
Output  
Input  
Pulse  
generator  
CL  
50  
Note: 1. CL includes probe and jig capacitance.  
Waveforms  
tr = 6 ns  
tf = 6 ns  
3 V  
90%  
90%  
1.3 V  
10%  
1.3 V  
10%  
Input  
GND  
VOH  
tTHL  
tTLH  
90%  
90%  
1.3 V  
10%  
1.3 V  
10%  
Output  
VOL  
tPHL  
tPLH  
Rev.5.00, Jan.28.2004, page 6 of 7  
 
HD74HCT1G04  
Package Dimensions  
Unit: mm  
1.3 ± 0.2  
+ 0.1  
– 0.05  
(0.65)  
(0.65)  
0.15  
0 – 0.1  
5 – 0.2 ± 0.05  
2.0 ± 0.2  
Package Code  
JEDEC  
CMPAK–5V  
JEITA  
Mass (reference value)  
Conforms  
0.006 g  
Rev.5.00, Jan.28.2004, page 7 of 7  
 
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Keep safety first in your circuit designs!  
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble  
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
Notes regarding these materials  
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's  
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.  
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therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product  
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The information described here may contain technical inaccuracies or typographical errors.  
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© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.  
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