Transcend Information Network Card TS2GSD150 User Manual

TS2GSD1  
50  
2GB 150x Secure Digital Card  
Description  
Features  
TS2GSD150 is a 2GB Secure Digital Card of 150X  
ultra-high performance. It is specifically designed to  
meet the security, capacity, performance and small  
form factor requirements in newly emerging audio  
and video consumer electronic devices. Based on  
dual channel technology and high quality SLC (Single  
Level Cell) NAND flash chip, TS2GSD150 is the ideal  
companion to bring out the most from your  
high-performance electronic devices.  
ROHS compliant product  
Operating Voltage: 2.7 ~ 3.6V  
Operating Temperature: -25 ~ 85°C  
Insertion/removal durability: 10,000 cycles  
Fully compatible with SD card spec. v1.1  
Mechanical Write Protection Switch  
Support clock frequencies: 0~50MHz  
Support different Bus width: x1, x4  
Support SD command class 0,2,4,5,7,8  
Supports Copy Protection for Recorded Media(CPRM) for  
music and other commercial media  
Placement  
Form Factor: 24mm x 32mm x 2.1mm  
Front  
Back  
Pin Definition  
SD Mode  
Description  
SPI Mode  
Pin No.  
Name Type  
Name Type  
Description  
Chip Select (neg true)  
Data In  
1
2
3
4
5
6
7
8
9
Card Detect/Data Line [Bit3]  
Command/Response  
Supply voltage ground  
Supply voltage  
I/O/PP  
CS  
DI  
I
CD/DAT3  
CMD  
VSS1  
PP  
S
S
I
I
Supply voltage ground  
Supply voltage  
Clock  
VSS  
VDD  
SCLK  
VSS2  
DO  
S
VDD  
S
CLK  
Clock  
I
S
VSS2  
S
Supply voltage ground  
Supply voltage ground  
Data Out  
DAT0 I/O/PP Data Line [Bit0]  
DAT1 I/O/PP Data Line [Bit1]  
O/PP  
RSV  
RSV  
I/O/PP Data Line [Bit2]  
DAT2  
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50  
2GB 150x Secure Digital Card  
Bus Protocol  
SD bus  
Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and  
terminated by a stop bit.  
Command: a command is a token which starts an operation. A command is sent from the host either to a single  
card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on  
the CMD line.  
Response: a response is a token which is sent from an addressed card, or (synchronously) from all connected  
cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD  
line.  
Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.  
Figure 4: “no response” and “no data” operations  
Card addressing is implemented using a session address, assigned to the card during the initializa-tion phase. The  
basic transaction on the SD bus is the command/response transaction (refer to Figure 4). This type of bus  
transactions transfer their information directly within the command or response structure. In addition, some  
operations have a data token.  
Data transfers to/from the SD Memory Card are done in blocks. Data blocks always succeeded by CRC bits. Single  
and multiple block operations are defined. Note that the Multiple Block operation mode is better for faster write  
operation. A multiple block transmission is terminated when a stop command follows on the CMD line. Data transfer  
can be configured by the host to use single or multiple data lines.  
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2GB 150x Secure Digital Card  
Figure 5: (Multiple) Block read operation  
The block write operation uses a simple busy signaling of the write operation duration on the DAT0 data line (see  
Figure 6) regardless of the number of data lines used for transferring the data.  
Figure 6: (Multiple) Block write operation  
Command tokens have the following coding scheme:  
Figure 7: Command token format  
Each command token is preceded by a start bit (‘0’) and succeeded by an end bit (‘1’). The total length is 48 bits.  
Each token is protected by CRC bits so that transmission errors can be detected and the operation may be repeated.  
Response tokens have four coding schemes depending on their content. The token length is either 48 or 136 bits.  
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2GB 150x Secure Digital Card  
The CRC protection algorithm for block data is a 16 bit CCITT polynomial.  
Figure 8: Response token format  
In the CMD line the MSB bit is transmitted first the LSB bit is the last.  
When the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 10). Start and end bits, as  
well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are calculated and checked for every  
DAT line individually. The CRC status response and Busy indica-tion will be sent by the card to the host on DAT0 only  
(DAT1-DAT3 during that period are don’t care).  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
SPI bus  
While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by  
a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to  
the CS signal (i.e. the length is a multiple of 8 clock cycles).  
Similar to the SD protocol, the SPI messages consist of command, response and data-block tokens All  
communication between host and cards is controlled by the host (master). The host starts every bus transaction by  
asserting the CS signal low.  
The response behavior in the SPI mode differs from the SD mode in the following three aspects:  
• The selected card always responds to the command.  
• Two new (8 & 16 bit) response structure is used  
• When the card encounters a data retrieval problem, it will respond with an error response (which replaces the  
expected data block) rather than by a time-out as in the SD mode.  
In addition to the command response, every data block sent to the card during write operations will be responded  
with a special data response token.  
• Data Read  
Single and multiple block read commands are supported in SPI mode. However, in order to comply with the SPI  
industry standard, only two (unidirectional) signal are used. Upon reception of a valid read command the card will  
respond with a response token followed by a data token of the length defined in a previous SET_BLOCKLEN  
(CMD16) command. A multiple block read operation is terminated, similar to the SD protocol, with the  
STOP_TRANSMISSION command.  
Figure 11: Read operation  
A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial X16 +X12 +X5 +1.  
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error token will be sent to  
the host Figure 12 shows a data read operation which terminated with an error token rather than a data block.  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
Figure 12: Read operation - data error  
• Data Write  
Single and multiple block write operations are supported in SPI mode. Upon reception of a valid write command, the  
card will respond with a response token and will wait for a data block to be sent from the host. CRC suffix, block  
length and start address restrictions are identical to the read operation (see Figure 13).  
Figure 13: Write operation  
After a data block has been received, the card will respond with a data-response token. If the data block has been  
received without errors, it will be programmed. As long as the card is busy programming, a continuous stream of busy  
tokens will be sent to the host (effectively holding the DataOut line low).  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
Card Registers  
1. OCR Register  
The 32-bit operation conditions register stores the VDD voltage profile of the card. In addition, this register includes a  
status information bit. This status bit is set if the card power up procedure has been finished. The OCR register shall  
be implemented by all cards. The supported voltage range is coded as shown in the following table. As long as the  
card is busy, the corresponding bit (31) is set to LOW.  
OCR bit  
[6:0]  
VDD voltage window  
Reserved  
SD  
000 0000 b  
0 b  
[7]  
1.65V – 1.95V  
2.0V – 2.6V  
[14:8]  
[23:15]  
[30:24]  
[31]  
000 0000 b  
1 1111 1111 b  
000 0000 b  
2.7V – 3.6V  
Reserved  
Card power status bit  
(1) OCR bit [31] is set to LOW if the card has not finished the power up routine.  
2. Card Identification Register (CID)  
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the  
card identification phase. Every individual flash or I/O card shall have an unique identification number. The structure  
of the CID register is defined in the following  
table  
3. Driver Stage Register (DSR)  
The 16-bit driver stage register is optionally used to improve the bus performance for extended operating  
conditions.The CSD register carries the information about the DSR register usage. This register is not implemented  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
4. Relative Card Address Register (RCA)  
The writable 16-bit relative card address register carries the card address assigned by the host during the card  
identification. This address is used for the addressed host-card communication after the card identification procedure.  
The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all cards into the Stand-by State  
with CMD7. In SD mode, the value of this register is generated by random number generator inside the card. Please  
reference to SD specification for detail information.  
5. Card Specific Data Register (CSD)  
The Card-Specific Data register provides information on how to access the card contents. The CSD defines the data  
format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used  
etc. The programmable part of the register can be changed by CMD27.  
CSD bit  
[127:126]  
[125:120]  
[119:112]  
[111:104]  
[103:96]  
[95:84]  
[83:80]  
[79]  
Width  
2
Name  
Field  
CSD_STRUCTURE  
---  
Value  
00 b  
---  
Note  
v1.0  
CSD structure  
6
Reserved  
---  
8
Data read access-time 1  
Data read access-time 2  
Max. bus clock freq.  
Card command classes  
Max. read data block length  
Partial block read allowed  
Write block misalignment  
Read block misalignment  
DSR implemented  
TAAC  
7F h  
FF h  
32 h  
1F5 h  
9 h  
80 ms  
25.5k clocks  
25 MHz  
(*1)  
8
NSAC  
8
TRAN_SPEED  
CCC  
12  
4
READ_BL_LEN  
READ_BL_PARTIAL  
WRITE_BLK_MISALIGN  
READ_BLK_MISALIGN  
DSR_IMP  
512 bytes  
Support  
Support  
Support  
Not support  
---  
1
1 b  
[78]  
1
1 b  
[77]  
1
1 b  
[76]  
1
0 b  
[75:74]  
[73:62]  
[61:59]  
[58:56]  
[55:53]  
[52:50]  
[49:47]  
[46]  
2
Reserved  
---  
---  
12  
3
Device size  
C_SIZE  
(*2)  
101 b  
101 b  
101 b  
101 b  
(*2)  
0 b  
(*2)  
Max. R_curr @ VDD min  
Max R_curr @ VDD max  
Max W_curr @ VDD min  
Max W_curr @ VDD max  
Device size multiplier  
Erase single block enable  
Erase sector size  
VDD_R_CURR_MIN  
VDD_R_CURR_MAX  
VDD_W_CURR_MIN  
VDD_W_CURR_MAX  
C_SIZE_MULT  
ERASE_BLK_EN  
SECTOR_SIZE  
WP_GRP_SIZE  
WP_GRP_ENABLE  
---  
35 mA  
45 mA  
35 mA  
45 mA  
(*2)  
3
3
3
3
1
Not allowed  
(*3)  
[45:39]  
[38:32]  
[31]  
7
(*3)  
(*4)  
1 b  
7
Write protect group size  
Write protect group enable  
Reserved  
(*4)  
1
Support  
---  
[30:29]  
[28:26]  
[25:22]  
[21]  
2
---  
3
Write speed factor  
R2W_FACTOR  
WRITE_BL_LEN  
WRITE_BL_PARTIAL  
---  
101 b  
9 h  
32X  
4
Max. write data block length  
Partial block write allowed  
Reserved  
512 bytes  
Support  
---  
1
1 b  
[20:16]  
[15]  
5
---  
1
File format group  
FILE_FORMAT_GRP  
0 b  
HD like FAT  
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50  
2GB 150x Secure Digital Card  
[14]  
[13]  
1
1
1
2
2
7
1
Copy flag  
COPY  
0 b  
0 b  
Not copied  
Not protected  
Not protected  
HD like FAT  
None  
Permanent write protection PERM_WRITE_PROTECT  
[12]  
Temporary write protection  
File format  
TMP_WRITE_PROTECT  
0 b  
[11:10]  
[9:8]  
[7:1]  
[0]  
FILE_FORMAT  
00 b  
00 b  
---  
ECC code  
ECC  
CRC  
---  
CRC  
---  
Not used always 1  
1 b  
---  
(*1) Support command class 0,2,4,5,6,7,8. Include : Basic, Block read/write, Erase, Write protection, application  
command, and Lock card. Not support 1,3. Include : Stream read/write.  
(*2)~(*4) This field is not a constant value. The value will be changed by different flash memory.  
6. Extended CSD Register (EXT_CSD)  
The Extended CSD register defines the card properties and selected modes. It is 512 bytes long.  
The most significant 320 bytes are the Properties segment, which defines the card capabilities and cannot be  
modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration the card is  
working in. These modes can be changed by the host by means of the SWITCH command.  
7. SD card Configuration Register (SCR)  
The CSD register is another configuration register in SD card. SCR provides on SD card s special features that were  
configured into the given card. The size of SCR is 64 bit.  
For SD card only. SCR is a read only register.  
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50  
2GB 150x Secure Digital Card  
AC/DC Character  
General  
Parameter  
Peak voltage on all lines  
All Inputs  
Symbol  
Min.  
-0.3  
Max.  
Unit  
V
Remark  
VDD+0.3  
Input Leakage Current  
All Outputs  
-10  
-10  
10  
10  
µA  
µA  
Output Leakage Current  
Power Supply Voltage  
Parameter  
Symbol  
VDD  
Min.  
2.0  
Max.  
3.6  
Unit  
V
Remark  
CMD0, 15,55,ACMD41  
commands  
Supply voltage  
Supply voltage specified in OCR register  
2.7  
3.6  
V
Except CMD0, 15,55,  
ACMD41 commands  
Supply voltage differentials (VSS1, VSS2  
)
-0.3  
0.3  
V
Power up time  
250  
ms  
From 0v to VDD Min.  
Bus Signal Line Load  
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus  
capacitance CBUS itself and the capacitance CCARD of each card connected to this line:  
CL = CHOST + CBUS + Ν*CCARD  
Parameter  
Bus signal line capacitance  
Single card capacitance  
Symbol  
CL  
Min.  
10  
Max.  
100  
10  
Unit  
pF  
Remark  
fPP 20 MHz, 7 cards  
CCARD  
pF  
Maximum signal line inductance  
Pull-up resistance inside card (pin1)  
16  
nH  
kΩ  
fPP 20 MHz  
RDAT3  
90  
May be used for card  
detection  
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only since they are  
connected separately to the SD Memory Card host.  
Parameter  
Pull-up resistance  
Symbol  
RCMD, RDAT  
CL  
Min.  
10  
Max.  
100  
Unit  
kΩ  
Remark  
To prevent bus floating  
fPP 5 MHz, 21 cards  
Bus signal line capacitance  
250  
pF  
11  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
Bus Signal Levels  
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.  
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages shall be within the  
following specified ranges for any VDD of the allowed voltage range:  
Parameter  
Output HIGH voltage  
Output LOW voltage  
Input HIGH voltage  
Input LOW voltage  
Symbol  
VOH  
Min.  
Max.  
Unit  
V
Remark  
0.75* VDD  
IOH = -100 μA @VDD min  
IOL = -100 μA @VDD min  
VOL  
0.125* VDD  
VDD + 0.3  
0.25* VDD  
V
VIH  
0.625* VDD  
V
VIL  
VSS – 0.3  
V
12  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
Bus Timing (Default)  
Parameter  
Symbol  
Min  
Max.  
Unit  
Remark  
Clock CLK (All values are referred to min (VIH) and max (VIL)  
Clock frequency Data Transfer Mode  
Clock frequency Identification Mode  
(The low freq. is required for MultiMediaCard  
compatibility.)  
fPP  
fOD  
0
0
25  
MHz CL 100 pF, (7 cards)  
400  
KHz CL 250 pF, (21 cards)  
Clock low time  
tWL  
tWH  
tTLH  
10  
50  
10  
50  
ns  
ns  
ns  
ns  
ns  
CL 100 pF, (7 cards)  
CL 250 pF, (21 cards)  
CL 100 pF, (7 cards)  
CL 250 pF, (21 cards)  
CL 100 pF, (7 cards)  
Clock high time  
Clock rise time  
10  
13  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
50  
10  
50  
ns  
ns  
ns  
CL 250 pF, (21 cards)  
CL 100 pF, (7 cards)  
CL 250 pF, (21 cards)  
Clock fall time  
tTHL  
Inputs CMD, DAT (referenced to CLK)  
Input set-up time  
tISU  
tIH  
5
5
ns  
ns  
CL 25 pF, (1 cards)  
Input hold time  
CL 25 pF, (1 cards)  
Outputs CMD, DAT (referenced to CLK)  
Output Delay time during Data Transfer Mode  
Output Delay time during Identification Mode  
tODLY  
tODLY  
0
0
14  
50  
ns  
ns  
CL 25 pF, (1 cards)  
CL 25 pF, (1 cards)  
14  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
Bus Timing (High Speed Mode)  
Parameter  
Symbol  
Min  
Max.  
50  
Unit  
Remark  
Clock CLK (All values are referred to min (VIH) and max (VIL)  
Clock frequency Data Transfer Mode  
Clock low time  
fPP  
0
7
MHz  
ns  
tWL  
Clock high time  
tWH  
tTLH  
tTHL  
7
ns  
ns  
ns  
Clock rise time  
3
3
Clock fall time  
Inputs CMD, DAT (referenced to CLK)  
Input set-up time  
tISU  
tIH  
6
2
ns  
ns  
Input hold time  
Outputs CMD, DAT (referenced to CLK)  
15  
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TS2GSD1  
50  
2GB 150x Secure Digital Card  
Output Delay time during Data Transfer Mode  
Output Hold time  
tODLY  
tOH  
14  
40  
ns  
ns  
pF  
2.5  
Total System capacitance for each line  
CL  
16  
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Reliability and Durability  
Temperature  
Operation: -25°C / 85°C (Target spec)  
Storage: -40°C (168h) / 85°C (500h)  
Junction temperature: max. 95°C  
Operation: 25°C / 95% rel. humidity  
Storage: 40°C / 93% rel. hum./500h  
Moisture and corrosion  
Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009  
Durability  
10.000 mating cycles;  
Bending  
10N  
Torque  
0.15N.m or +/-2.5 deg  
Drop test  
1.5m free fall  
UV light exposure  
Visual inspection  
Shape and form  
UV: 254nm, 15Ws/cm² according to ISO 7816-1  
No warp page; no mold skin; complete form; no cavities surface smoothness <=  
-0.1 mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc.)  
Minimum moving force of WP witch 40gf  
WP Switch cycles  
minimum 1000 Cycles(@Slide force 0.4N to 5N)  
Above technical information is based on SD1.1 standard specification and tested to be reliable. However, Transcend  
makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of  
this product. Transcend reserves the right to make changes in specifications at any time without prior notice.  
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