Cypress Computer Hardware CY7C1223H User Manual

CY7C1223H  
2-Mbit (128K x 18) Pipelined DCD Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
— Depth expansion without wait state  
• 128K × 18-bit common I/O architecture  
• 3.3V core power supply  
The CY7C1223H SRAM integrates 128K x 18 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE ), depth-expansion Chip Enables (CE and CE ), Burst  
1
2
3
• 3.3V/2.5V I/O supply  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
[A:B]  
• Fast clock-to-output time  
— 3.5 ns (for 166-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
— 4.0 ns (for 133-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
®
• User-selectable burst counter supporting Intel  
®
Pentium interleaved or linear burst sequences  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two bytes wide as  
controlled by the byte write control inputs. GW active LOW  
causes all bytes to be written. This device incorporates an  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous Output Enable  
• Offered in JEDEC-standard lead-free 100-pin TQFP  
package  
• “ZZ” Sleep Mode option  
The CY7C1223H operates from a +3.3V core power supply  
while all outputs operate with either a +3.3V/2.5V supply. All  
inputs and outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
240  
225  
mA  
mA  
Maximum CMOS Standby Current  
40  
40  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05674 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 6, 2006  
 
CY7C1223H  
Pin Configurations  
100-pin TQFP Pinout  
Top View  
NC  
NC  
1
2
3
4
5
6
7
8
80  
79  
78  
A
NC  
NC  
NC  
VDDQ  
VSSQ  
NC  
NC  
DQB  
DQB  
VSSQ  
VDDQ  
DQB  
DQB  
NC  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VDDQ  
VSSQ  
NC  
DQPA  
DQA  
DQA  
VSSQ  
VDDQ  
DQA  
DQA  
VSS  
NC  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDD  
CY7C1223H  
NC  
VDD  
ZZ  
VSS  
DQB  
DQB  
VDDQ  
VSSQ  
DQB  
DQB  
DQPB  
DQA  
DQA  
VDDQ  
VSSQ  
DQA  
DQA  
NC  
NC  
NC  
VSSQ  
VSSQ  
VDDQ  
NC  
NC  
NC  
VDDQ  
NC  
NC  
NC  
Document #: 38-05674 Rev. *B  
Page 3 of 16  
 
CY7C1223H  
Pin Descriptions  
Pin  
A0, A , A  
Type  
Input-  
Synchronous edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE are sampled active.  
Description  
Address Inputs used to select one of the 128K address locations. Sampled at the rising  
1
1
2
3
A
are fed to the two-bit counter.  
[1:0]  
BW  
Input-  
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.  
[A:B]  
Synchronous Sampled on the rising edge of CLK.  
GW  
Input-  
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a  
Synchronous global write is conducted (ALL bytes are written, regardless of the values on BW  
and BWE).  
[A:B]  
BWE  
CLK  
Input-  
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must  
Synchronous be asserted LOW to conduct a byte write.  
Input-  
Clock  
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the  
burst counter when ADV is asserted LOW, during a burst operation.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
1
2
3
Synchronous with CE and CE to select/deselect the device. ADSP is ignored if CE is HIGH.  
CE  
is sampled  
2
3
1
1
only when a new external address is loaded.  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device. CE  
Input-  
is sampled only when a new external  
1
3
2
address is loaded.  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction  
Synchronous with CE and CE to select/deselect the device. CE is sampled only when a new external  
Input-  
1
2
3
address is loaded  
OE  
Input-  
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When  
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act  
as input data pins. OE is masked during the first clock of a read cycle when emerging from a  
deselected state.  
ADV  
Input-  
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it  
Synchronous automatically increments the address in a burst cycle.  
ADSP  
Input- Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A  
[1:0]  
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP  
is recognized. ASDP is ignored when CE is deasserted HIGH.  
1
ADSC  
Input-  
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When  
Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A  
[1:0]  
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP  
is recognized.  
ZZ  
Input-  
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical  
Asynchronous “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or  
left floating. ZZ pin has an internal pull-down.  
DQs  
DQP  
I/O-  
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered  
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location  
specified by the addresses presented during the previous clock rise of the read cycle. The  
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.  
[A:B]  
When HIGH, DQs and DQP  
are placed in a tri-state condition.  
[A:B]  
V
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
Ground  
Ground for the core of the device.  
Power supply for the I/O circuitry.  
SS  
I/O Power  
Supply  
DDQ  
V
I/O Ground  
Ground for the I/O circuitry.  
SSQ  
MODE  
Input-  
Static  
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V or left  
floating selects interleaved burst sequence. This is a strap pin and should remain static during  
DD  
device operation. Mode Pin has an internal pull-up.  
NC  
No Connects. Not internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M, and  
1G are address expansion pins and are not internally connected to the die.  
Document #: 38-05674 Rev. *B  
Page 4 of 16  
 
CY7C1223H  
then the write operation is controlled by BWE and BW  
Functional Overview  
[A:B]  
signals. The CY7C1223H provides Byte Write capability that  
is described in the Write Cycle Description table. Asserting the  
Byte Write Enable input (BWE) with the selected Byte Write  
input will selectively write to only the desired bytes. Bytes not  
selected during a Byte Write operation will remain unaltered.  
A synchronous self-timed write mechanism has been provided  
to simplify the Write operations.  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
The CY7C1223H supports secondary cache in systems  
utilizing either a linear or interleaved burst sequence. The  
interleaved burst order supports Pentium and i486™  
processors. The linear burst sequence is suited for processors  
that utilize a linear burst sequence. The burst order is user  
selectable, and is determined by sampling the MODE input.  
Because the CY7C1223H is a common I/O device, the Output  
Enable (OE) must be deasserted HIGH before presenting data  
to the DQ inputs. Doing so will tri-state the output drivers. As  
a safety precaution, DQ are automatically tri-stated whenever  
a write cycle is detected, regardless of the state of OE.  
Accesses can  
Strobe (ADSP)  
be initiated with either the Processor Address  
or the Controller Address Strobe (ADSC).  
Address advancement through the burst sequence is  
controlled by the ADV input. A two-bit on-chip wraparound  
burst counter captures the first address in a burst sequence  
and automatically increments the address for the rest of the  
burst access.  
Single Write Accesses Initiated by ADSC  
ADSC write accesses are initiated when the following condi-  
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is  
deasserted HIGH, (3) chip select is asserted active, and (4)  
the appropriate combination of the write inputs (GW, BWE,  
Byte write operations are qualified with the Byte Write Enable  
and BW  
) are asserted active to conduct a write to the  
(BWE) and Byte Write Select (BW  
) inputs. A Global Write  
[A:B]  
[A:B]  
desired byte(s). ADSC triggered write accesses require a  
single clock cycle to complete. The address presented is  
loaded into the address register and the address  
advancement logic while being delivered to the memory core.  
The ADV input is ignored during this cycle. If a global write is  
Enable (GW) overrides all byte write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self-timed write circuitry.  
Synchronous Chip Selects CE , CE , CE and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
conducted, the data presented to the DQ is written into the  
X
selection and output tri-state control. ADSP is ignored if CE  
1
corresponding address location in the memory core. If a byte  
write is conducted, only the selected bytes are written. Bytes  
not selected during a byte write operation will remain  
unaltered. A synchronous self-timed write mechanism has  
been provided to simplify the write operations.  
is HIGH.  
Single Read Accesses  
This access is initiated when the following conditions are  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
chip selects are all asserted active, and (3) the Write signals  
Because the CY7C1223H is a common I/O device, the Output  
Enable (OE) must be deasserted HIGH before presenting data  
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE  
1
to the DQ inputs. Doing so will tri-state the output drivers. As  
X
is HIGH. The address presented to the address inputs is  
stored into the address advancement logic and the Address  
Register while being presented to the memory core. The corre-  
sponding data is allowed to propagate to the input of the  
Output Registers. At the rising edge of the next clock the data  
is allowed to propagate through the output register and onto  
a
safety precaution, DQ are automatically tri-stated  
X
whenever a write cycle is detected, regardless of the state of  
OE.  
Burst Sequences  
the data bus within t if OE is active LOW. The only exception  
CO  
The CY7C1223H provides a two-bit wraparound counter, fed  
occurs when the SRAM is emerging from a deselected state  
to a selected state, its outputs are always tri-stated during the  
first cycle of the access. After the first cycle of the access, the  
outputs are controlled by the OE signal. Consecutive single  
read cycles are supported.  
by A  
, that implements either an interleaved or linear burst  
[1:0]  
sequence. The interleaved burst sequence is designed specif-  
ically to support Intel Pentium applications. The linear burst  
sequence is designed to support processors that follow a  
linear burst sequence. The burst sequence is user selectable  
through the MODE input. Both read and write burst operations  
are supported.  
The CY7C1223H is a double-cycle deselect part. Once the  
SRAM is deselected at clock rise by the chip select and either  
ADSP or ADSC signals, its output will tri-state immediately  
after the next clock rise.  
Asserting ADV LOW at clock rise will automatically increment  
the burst counter to the next address in the burst sequence.  
Both read and write burst operations are supported.  
Single Write Accesses Initiated by ADSP  
This access is initiated when both of the following conditions  
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)  
chip select is asserted active. The address presented is  
loaded into the address register and the address  
advancement logic while being delivered to the memory core.  
Sleep Mode  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
the “sleep” mode. CEs, ADSP, and ADSC must remain  
The write signals (GW, BWE, and BW  
ignored during this first cycle.  
) and ADV inputs are  
[A:B]  
ADSP triggered write accesses require two clock cycles to  
complete. If GW is asserted LOW on the second clock rise, the  
data presented to the DQx inputs is written into the corre-  
sponding address location in the memory core. If GW is HIGH,  
inactive for the duration of t  
LOW.  
after the ZZ input returns  
ZZREC  
Document #: 38-05674 Rev. *B  
Page 5 of 16  
 
CY7C1223H  
Linear Burst Address Table (MODE = GND)  
Interleaved Burst Address Table (MODE = Floating or V  
)
DD  
First  
Address  
A1, A0  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
First  
Address  
A1, A0  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
00  
01  
10  
11  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
Truth Table [2, 3, 4, 5, 6]  
Address  
Operation  
Used CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK  
DQ  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Q
1
2
3
Deselected Cycle, Power-down None  
Deselected Cycle, Power-down None  
Deselected Cycle, Power-down None  
Deselected Cycle, Power-down None  
Deselected Cycle, Power-down None  
H
L
X
L
X
X
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H  
L-H  
L-H  
L-H  
L-H  
X
L
X
L
L
L
H
H
X
L
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
ZZ Mode, Power-down  
None  
External  
External  
External  
External  
External  
Next  
X
L
X
X
X
L
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Write Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L-H  
L
L
L
H
X
L
Tri-State  
D
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
L
L
L
H
L
Tri-State  
Q
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next  
L
H
L
Tri-State  
Q
Next  
L
Next  
L
H
X
X
L
Tri-State  
D
Next  
L
Next  
L
L
D
Current  
Current  
Current  
Current  
Current  
Current  
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
Tri-State  
Q
H
X
X
Tri-State  
D
Write Cycle, Suspend Burst  
L
D
Notes:  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.  
3. WRITE = L when any one or more Byte Write enable signals (BW , BW and BWE = L or GW = L. WRITE = H when all Byte write enable signals (  
,
)
B
BW BW ),  
A
A
B
, GW=H.  
BWE  
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW  
. Writes may occur only on subsequent clocks  
[A:B]  
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a  
don't care for the remainder of the write cycle.  
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is  
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).  
Document #: 38-05674 Rev. *B  
Page 6 of 16  
 
CY7C1223H  
Truth Table for Read/Write[2, 3]  
Function  
GW  
H
BWE  
BW  
BW  
X
A
B
Read  
Read  
H
L
L
L
L
X
X
H
L
H
H
H
L
Write byte A - (DQ and DQP )  
H
A
A
Write byte B- (DQ and DQP )  
H
H
L
B
B
Write all bytes  
Write all bytes  
H
L
L
X
X
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
Min.  
Max.  
40  
Unit  
mA  
ns  
I
t
t
t
t
ZZ > V 0.2V  
DD  
DDZZ  
ZZ > V 0.2V  
2t  
ZZS  
DD  
CYC  
ZZ < 0.2V  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
ZZ inactive to exit sleep current  
0
ns  
RZZI  
Document #: 38-05674 Rev. *B  
Page 7 of 16  
 
CY7C1223H  
DC Input Voltage ..................................... –0.5V to V +0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20mA  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883,Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Storage Temperature .................................... –65°C to +150°  
Latch-up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Range Temperature (T )  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
DD  
DDQ  
V
V
DDQ  
A
DD  
DC Voltage Applied to Outputs  
in tri-state ............................................ –0.5V to V  
Com’l  
Ind’l  
0°C to +70°C  
3.3V 5%/+10% 2.5V5% to  
+0.5V  
DDQ  
V
DD  
–40°C to +85°C  
[7, 8]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
3.135  
3.135  
2.375  
2.4  
Max.  
Unit  
V
V
V
3.6  
DD  
for 3.3V I/O  
for 2.5V I/O  
V
V
DDQ  
DD  
2.625  
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
for 3.3V I/O, I = –4.0 mA  
V
V
OH  
OL  
IH  
OH  
for 2.5V I/O, I = –1.0 mA  
2.0  
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
OL  
for 2.5V I/O, I = 1.0 mA  
OL  
[7]  
Input HIGH Voltage  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
GND V V  
2.0  
1.7  
V
+ 0.3V  
+ 0.3V  
V
V
DD  
V
DD  
[7]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
0.8  
0.7  
5
V
IL  
V
Input Leakage Current  
except ZZ and MODE  
µA  
X
I
DDQ  
Input Current of MODE  
Input = V  
Input = V  
Input = V  
Input = V  
–30  
–5  
µA  
µA  
SS  
DD  
SS  
DD  
5
Input Current of ZZ  
µA  
30  
5
µA  
I
I
Output Leakage Current GND V V  
Output Disabled  
–5  
µA  
OZ  
I
DDQ,  
V
Operating Supply  
V
f = f  
= Max., I  
= 0 mA,  
6-ns cycle, 166 MHz  
7.5-ns cycle,133MHz  
240  
225  
100  
90  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
= 1/t  
MAX CYC  
Current  
I
I
I
Automatic CS  
Power-down  
Current—TTL Inputs  
V
=Max.,DeviceDeselected, 6-ns cycle, 166 MHz  
DD  
SB1  
V
V or V V ,  
IN  
IH  
IN  
IL  
7.5-ns cycle,133MHz  
f = f  
= 1/t  
MAX CYC  
Automatic CS  
Power-down  
Current—CMOS Inputs  
V = Max., Device Deselected, All speeds  
DD  
40  
mA  
SB2  
SB3  
V
0.3V or V > V  
– 0.3V,  
IN  
IN  
DDQ  
f = 0  
Automatic CS  
Power-down  
Current—CMOS Inputs  
V
= Max., Device Deselected, 6.0-ns cycle, 166 MHz  
85  
75  
mA  
mA  
DD  
or V 0.3V or  
IN  
> V  
7.5-ns cycle, 133MHz  
V
– 0.3V,  
IN  
DDQ  
f = f  
= 1/t  
CYC  
MAX  
I
Automatic CS  
Power-down  
Current—TTL Inputs  
V
= Max., Device Deselected, All speeds  
DD  
45  
mA  
SB4  
V
V or V V , f = 0  
IN  
IH IN IL  
Notes:  
7. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t /2).  
CYC  
IH  
DD  
CYC  
IL  
8. Power-up: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
DD  
IH  
DD  
DDQ  
DD  
Document #: 38-05674 Rev. *B  
Page 8 of 16  
 
CY7C1223H  
Capacitance[9]  
100 TQFP  
Max.  
Parameter  
Description  
Input Capacitance  
Test Conditions  
Unit  
pF  
C
T = 25°C, f = 1 MHz,  
5
5
5
IN  
A
V
= 3.3V  
= 2.5V  
DD  
C
C
Clock Input Capacitance  
Input/Output Capacitance  
pF  
CLK  
I/O  
V
DDQ  
pF  
Thermal Characteristics[9]  
100 TQFP  
Package  
Parameter  
Description  
Thermal Resistance  
(Junction to Ambient)  
Test Conditions  
Unit  
ΘJA  
Test conditions follow standard  
test methods and procedures for  
measuring thermal impedance,  
per EIA/JESD51  
30.32  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to case)  
6.85  
°C/W  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
10%  
R = 50Ω  
L
5 pF  
R = 351Ω  
1 ns  
1 ns  
INCLUDING  
JIG AND  
SCOPE  
V = 1.5V  
T
(a)  
(c)  
(b)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
90%  
10%  
Z = 50Ω  
0
10%  
L
GND  
5 pF  
R =1538Ω  
1 ns  
1 ns  
INCLUDING  
V = 1.25V  
T
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Note:  
9. Tested initially and after any design or process change that may affect these parameters.  
Document #: 38-05674 Rev. *B  
Page 9 of 16  
 
CY7C1223H  
[14, 15]  
Switching Characteristics Over the Operating Range  
166 MHz  
133 MHz  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
[10]  
t
V
(Typical) to the first Access  
1
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
6.0  
2.5  
2.5  
7.5  
3.0  
3.0  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
3.5  
4.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CO  
1.5  
0
1.5  
0
DOH  
CLZ  
[11, 12, 13]  
Clock to Low-Z  
[11, 12, 13]  
Clock to High-Z  
3.5  
3.5  
4.0  
4.0  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[11, 12, 13]  
OE LOW to Output Low-Z  
0
0
[11, 12, 13]  
OE HIGH to Output High-Z  
3.5  
4.0  
Set-up Times  
t
t
t
t
t
t
Address Set-up Before CLK Rise  
ADSC, ADSP Set-up Before CLK Rise  
ADV Set-up Before CLK Rise  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ns  
AS  
ADS  
ADVS  
WES  
DS  
GW, BWE, BW  
Set-up Before CLK Rise  
[A:B]  
Data Input Set-up Before CLK Rise  
Chip Enable Set-up Before CLK Rise  
CES  
Hold Times  
t
t
t
t
t
t
Address Hold After CLK Rise  
ADSP , ADSC Hold After CLK Rise  
ADV Hold After CLK Rise  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
AH  
ADH  
ADVH  
WEH  
DH  
GW,BWE, BW  
Hold After CLK Rise  
[A : B]  
Data Input Hold After CLK Rise  
Chip Enable Hold After CLK Rise  
CEH  
Notes:  
10. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V minimum initially before a read or write operation  
DD  
can be initiated.  
11. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
OEHZ  
CHZ CLZ OELZ  
12. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
OEHZ  
OELZ  
CHZ  
CLZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve High-Z prior to Low-Z under the same system conditions.  
13. This parameter is sampled and not 100% tested.  
14. Timing reference level is 1.5V when V  
= 3.3V and 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.  
Document #: 38-05674 Rev. *B  
Page 10 of 16  
 
CY7C1223H  
Switching Waveforms  
[16]  
Read Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
ADH  
ADS  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Burst continued with  
new base address  
t
t
WEH  
WES  
GW, BWE,BW[A:B]  
Deselect  
cycle  
t
t
CEH  
CES  
CE  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
OEV  
CO  
t
t
CHZ  
t
t
t
OELZ  
OEHZ  
DOH  
CLZ  
t
Q(A2)  
Q(A2 + 1)  
Q(A2 + 2)  
Q(A2 + 3)  
Q(A2)  
Q(A2 + 1)  
Q(A3)  
Q(A1)  
Data Out (Q)  
High-Z  
CO  
Burst wraps around  
to its initial state  
Single READ  
BURST READ  
DON’T CARE  
UNDEFINED  
Note:  
16. On this diagram, when CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
Document #: 38-05674 Rev. *B  
Page 11 of 16  
 
CY7C1223H  
Switching Waveforms (continued)  
[16, 17]  
Write Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC extends burst  
t
t
ADH  
ADS  
t
t
ADH  
ADS  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
ADDRESS  
Byte write signals are ignored for first cycle when  
ADSP initiates burst  
t
t
WEH  
WES  
BWE,  
BW[A:B]  
t
t
WEH  
WES  
GW  
CE  
t
t
CEH  
CES  
t
t
ADVH  
ADVS  
ADV  
OE  
ADV suspends burst  
t
t
DH  
DS  
D(A2)  
D(A2 + 1)  
D(A2 + 1)  
D(A2 + 2)  
D(A2 + 3)  
D(A3)  
D(A3 + 1)  
D(A3 + 2)  
D(A1)  
High-Z  
Data in (D)  
t
OEHZ  
Data Out (Q)  
BURST READ  
Single WRITE  
BURST WRITE  
DON’T CARE  
Extended BURST WRITE  
UNDEFINED  
Note:  
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW  
LOW.  
17.  
[A:B]  
Document #: 38-05674 Rev. *B  
Page 12 of 16  
 
CY7C1223H  
Switching Waveforms (continued)  
[16, 18, 19]  
Read/Write Timing  
t
CYC  
CLK  
t
t
CL  
CH  
t
t
ADH  
ADS  
ADSP  
ADSC  
t
t
AH  
AS  
A1  
A2  
A3  
A4  
A5  
A6  
ADDRESS  
t
t
WEH  
WES  
BWE, BW[A:B]  
t
t
CEH  
CES  
CE  
ADV  
OE  
t
t
DH  
t
CO  
DS  
t
OELZ  
Data In (D)  
High-Z  
High-Z  
D(A3)  
D(A5)  
D(A6)  
t
t
OEHZ  
CLZ  
Data Out (Q)  
Q(A1)  
Back-to-Back READs  
Q(A2)  
Q(A4)  
Q(A4+1)  
Q(A4+2)  
Q(A4+3)  
Single WRITE  
DON’T CARE  
BURST READ  
Back-to-Back  
WRITEs  
UNDEFINED  
Notes:  
18. The data bus (Q) remains in High-Z following a Write cycle, unless a new read access initiated by ADSC or ADSP.  
19. GW is HIGH.  
Document #: 38-05674 Rev. *B  
Page 13 of 16  
 
CY7C1223H  
Switching Waveforms (continued)  
[20,21]  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
20. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.  
21. DQs are in High-Z when exiting ZZ sleep mode.  
Document #: 38-05674 Rev. *B  
Page 14 of 16  
 
CY7C1223H  
Ordering Information  
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered”.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1223H-166AXC  
CY7C1223H-166AXI  
CY7C1223H-133AXC  
CY7C1223H-133AXI  
Package Type  
166  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
Industrial  
133  
Commercial  
Industrial  
Package Diagram  
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
0.20 MIN.  
51-85050-*B  
1.00 REF.  
DETAIL  
A
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark  
of IBM. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05674 Rev. *B  
Page 15 of 16  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.  
CY7C1223H  
Document History Page  
Document Title: CY7C1223H 2-Mbit (128K x 18) Pipelined DCD Sync SRAM  
Document Number: 38-05674  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
347357  
424820  
See ECN  
See ECN  
PCI  
New Data Sheet  
*A  
RXU  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed Three-State to Tri-State.  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table.  
Modified test condition from V < V to V < V  
IH  
DD  
IH  
DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table.  
Replaced Package Diagram of 51-85050 from *A to *B  
*B  
459347  
See ECN  
NXR  
Converted from Preliminary to Final  
Included 2.5V I/O option  
Updated the Ordering Information table.  
Document #: 38-05674 Rev. *B  
Page 16 of 16  
 

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