Intel Computer Hardware UPI C42 User Manual

UPI-C42/UPI-L42  
UNIVERSAL PERIPHERAL INTERFACE  
CHMOS 8-BIT SLAVE MICROCONTROLLER  
Y
Y
Y
Pin, Software and Architecturally  
One 8-Bit Status and Two Data  
Registers for Asynchronous Slave-to-  
Master Interface  
Compatible with all UPI-41 and UPI-42  
Products  
Y
Y
Low Voltage Operation with the UPI-  
L42  
Ð Full 3.3V Support  
Fully Compatible with all Intel and Most  
Other Microprocessor Families  
Interchangeable ROM and OTP EPROM  
Versions  
Y
Y
Y
Y
Hardware A20 Gate Support  
Y
Y
Y
Y
Suspend Power Down Mode  
Expandable I/O  
Security Bit Code Protection Support  
Sync Mode Available  
8-Bit CPU plus ROM/OTP EPROM, RAM,  
I/O, Timer/Counter and Clock in a  
Single Package  
Over 90 Instructions: 70% Single Byte  
Quick Pulse Programming Algorithm  
Ð Fast OTP Programming  
Y
Y
4096 x 8 ROM/OTP, 256 x 8 RAM 8-Bit  
Timer/Counter, 18 Programmable I/O  
Pins  
Y
Available in 40-Lead Plastic, 44-Lead  
Plastic Leaded Chip Carrier, and  
44-Lead Quad Flat Pack Packages  
Ý
(See Packaging Spec., Order 240800, Package Type P, N,  
and S)  
DMA, Interrupt, or Polled Operation  
Supported  
The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family. It is fabricated on  
Intel’s CHMOS III-E process. The UPI-C42 is pin, software, and architecturally compatible with the NMOS UPI  
family. The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory  
array (4K), hardware A20 gate support, and lower power consumption inherent to a CHMOS product.  
The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low  
voltage 3.3V operation.  
The UPI-C42 is essentially a ‘‘slave’’ microcontroller, or a microcontroller with a slave interface included on the  
chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the  
MCS Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems.  
To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM  
(OTP).  
290414–1  
290414–3  
Figure 1. DIP Pin  
290414–2  
Figure 3. QFP Pin Configuration  
Configuration  
Figure 2. PLCC Pin Configuration  
*Other brands and names are the property of their respective owners.  
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or  
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make  
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.  
©
COPYRIGHT INTEL CORPORATION, 1996  
December 1995  
Order Number: 290414-003  
 
UPI-C42/UPI-L42  
Table 1. Pin Description (Continued)  
DIP  
Pin  
No.  
PLCC  
Pin  
QFP  
Pin  
Symbol  
Type  
Name and Function  
No.  
No.  
P
20  
–P  
27  
2124 2427  
3942  
I/O  
PORT 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower 4 bits  
(P P ) interface directly to the 8243 I/O expander device and  
20  
3538 3942 11, 1315  
23  
contain address and data information during PORT 4–7 access. P  
21  
can be programmed to provide hardware A20 gate support. The upper  
4 bits (P P ) can be programmed to provide interrupt Request and  
24 27  
DMA Handshake capability. Software control can configure P as  
24  
Output Buffer Full (OBF) interrupt, P as Input Buffer Full (IBF)  
25  
interrupt, P as DMA Request (DRQ), and P as DMA ACKnowledge  
26 27  
(DACK).  
PROG  
25  
28  
43  
I/O  
PROGRAM: Multifunction pin used as the program pulse input during  
PROM programming.  
During I/O expander access the PROG pin acts as an address/data  
strobe to the 8243. This pin should be tied high if unused.  
a
POWER: 5V main power supply pin.  
V
V
40  
26  
44  
29  
17  
1
CC  
a
a
POWER: 5V during normal operation. 12.75V during programming  
operation. Low power standby supply pin.  
DD  
V
SS  
20  
22  
38  
GROUND: Circuit ground potential.  
290414–4  
Figure 4. Block Diagram  
3
 
UPI-C42/UPI-L42  
UPI-C42/L42 PRODUCT SELECTION GUIDE  
UPI-C42: Low power CHMOS version of the UPI-42.  
Device  
Package  
ROM  
OTP  
Comments  
80C42  
N, P S  
4K  
ROM Device  
82C42PC  
82C42PD  
82C42PE  
N, P, S  
N, P, S  
N, P, S  
Phoenix MultiKey/42 firmware, PS/2 style mouse support  
Phoenix MultiKey/42L firmware, KBC and SCC for portable apps.  
Phoenix MultiKey/42G firmware, Energy Efficient KBC solution  
87C42  
N, P, S  
4K  
One Time Programmable Version  
UPI-L42: The low voltage 3.3V version of the UPI-C42.  
Device  
Package  
ROM  
OTP  
Comments  
80L42  
N, P S  
4K  
ROM Device  
82L42PC  
82L42PD  
N, P, S  
N, P, S  
Phoenix MultiKey/42 firmware, PS/2 style mouse support  
Phoenix MultiKey/42L firmware, KBC and SCC for portable apps.  
87L42  
N, P, S  
4K  
One Time Programmable Version  
e
N
KBC  
e
Key Board Control, SCC  
e
Scan Code Control  
e
44 lead PLCC, P  
e
40 lead PDIP, S  
e
44 lead QFP, D  
40 lead CERDIP  
The 82C42PC provides a low powered solution for  
industry standard keyboard and PS/2 style mouse  
control. The 82C42PD provides a cost effective  
means for keyboard and scan code control for note-  
book platforms. The 82C42PE allows a quick time to  
market, low cost solution for energy efficient desk-  
top designs.  
THE INTEL 82C42  
As shown in the UPI-C42 product matrix, the UPI-  
C42 is offered as a pre-programmed 80C42 with var-  
ious versions of MultiKey/42 keyboard controller  
firmware developed by Phoenix Technologies Ltd.  
4
 
UPI-C42/UPI-L42  
4. P and P are port pins or Buffer Flag pins  
24  
25  
which can be used to interrupt a master proces-  
sor. These pins default to port pins on Reset.  
UPI-42 COMPATIBLE FEATURES  
1. Two Data Bus Buffers, one for input and one for  
output. This allows a much cleaner Master/Slave  
protocol.  
If the ‘‘EN FLAGS’’ instruction has been execut-  
ed, P becomes the OBF (Output Buffer Full)  
24  
pin. A ‘‘1’’ written to P enables the OBF pin (the  
24  
pin outputs the OBF Status Bit). A ‘‘0’’ written to  
P
24  
disables the OBF pin (the pin remains low).  
This pin can be used to indicate that valid data is  
available from the UPI (in Output Data Bus Buff-  
er).  
If ‘‘EN FLAGS’’ has been executed, P be-  
comes the IBF (Input Buffer Full) pin. A ‘‘1’’ writ-  
25  
ten to P enables the IBF pin (the pin outputs  
25  
the inverse of the IBF Status Bit. A ‘‘0’’ written to  
P
25  
disables the IBF pin (the pin remains low).  
This pin can be used to indicate that the UPI is  
ready for data.  
290414–5  
2. 8 Bits of Status  
Data Bus Buffer Interrupt Capability  
ST ST ST ST  
5
F
F
0
IBF OBF  
7
6
4
1
D
7
D
D
D
D
D
2
D
D
0
6
5
4
3
1
ST ST are user definable status bits. These  
4
7
bits are defined by the ‘‘MOV STS, A’’ single  
byte, single cycle instruction. Bits 4–7 of the  
acccumulator are moved to bits 4–7 of the status  
register. Bits 0–3 of the status register are not  
affected.  
290414–7  
MOV STS, A Op Code: 90H  
1
0
0
1
0
0
0
0
EN FLAGS Op Code: 0F5H  
D
7
D
0
1
1
1
1
0
1
0
1
D
D
0
3. RD and WR are edge triggered. IBF, OBF, F and  
1
7
INT change internally after the trailing edge of RD  
or WR.  
5. P and P are port pins or DMA handshake  
26  
27  
pins for use with a DMA controller. These pins  
default to port pins on Reset.  
During the time that the host CPU is reading the  
status register, the UPI is prevented from updat-  
ing this register or is ‘locked out.’  
If the ‘‘EN DMA’’ instruction has been executed,  
P
26  
written to P causes a DMA request (DRQ is  
becomes the DRQ (DMA Request) pin. A ‘‘1’’  
26  
activated). DRQ is deactivated by DACK RD,  
DACK WR, or execution of the ‘‘EN DMA’’ in-  
#
#
struction.  
290414–6  
DMA Handshake Capability  
290414–8  
5
 
UPI-C42/UPI-L42  
If ‘‘EN DMA’’ has been executed, P becomes  
27  
PROGRAM MEMORY BANK SWITCH  
the DACK (DMA ACKnowledge) pin. This pin acts  
as a chip select input for the Data Bus Buffer  
registers during DMA transfers.  
The switching of 2K program memory banks is ac-  
complished by directly setting or resetting the most  
significant bit of the program counter (bit 11); see  
Figure 5. Bit 11 is not altered by normal increment-  
ing of the program counter, but is loaded with the  
contents of a special flip-flop each time a JMP or  
CALL instruction is executed. This special flip-flop is  
set by executing an SEL PMB1 instruction and reset  
by SEL PMB0. Therefore, the SEL PMB instruction  
may be executed at any time prior to the actual bank  
switch which occurs during the next branch instruc-  
tion encountered. Since all twelve bits of the pro-  
gram counter, including bit 11, are stored in the  
stack, when a Call is executed, the user may jump to  
subroutines across the 2K boundary and the proper  
PC will be restored upon return. However, the bank  
switch flip-flop will not be altered on return.  
EN DMA Op Code: 0E5H  
1
1
1
0
0
1
0
1
D
7
D
0
6. When EA is enabled on the UPI, the program  
counter is placed on Port 1 and the lower four  
e
e
bits of Port 2 (MSB  
P , LSB  
23  
P ). On the  
10  
UPI this information is multiplexed with PORT  
DATA (see port timing diagrams at end of this  
data sheet).  
7. The UPI-C42 supports the Quick Pulse Program-  
ming Algorithm, but can also be programmed  
with the Intelligent Programming Algorithm. (See  
the Programming Section.)  
UPI-C42 FEATURES  
Programmable Memory Size Increase  
The user programmable memory on the UPI-C42 will  
be increased from the 2K available in the NMOS  
product by 2X to 4K. The larger user programmable  
memory array will allow the user to develop more  
complex peripheral control micro-code. P2.3 (port 2  
bit 3) has been designated as the extra address pin  
required to support the programming of the extra 2K  
of user programmable memory.  
29041430  
Figure 5. Program Counter  
The new instruction SEL PMB1 (73h) allows for ac-  
cess to the upper 2K bank (locations 20484095).  
The additional memory is completely transparent to  
users not wishing to take advantage of the extra  
memory space. No new commands are required to  
access the lower 2K bytes. The SEL PMB0 (63h)  
has also been added to the UPI-C42 instruction set  
to allow for switching between memory banks.  
INTERRUPT ROUTINES  
Interrupts always vector the program counter to lo-  
cation 3 or 7 in the first 2K bank, and bit 11 of the  
program counter is held at ‘‘0’’ during the interrupt  
service routine. The end of the service routine is sig-  
naled by the execution of an RETR instruction. Inter-  
rupt service routines should therefore be contained  
entirely in the lower 2K words of program memory.  
The execution of a SEL PMB0 or SEL PMB1 instruc-  
tion within an interrupt routine is not recommended  
since it will not alter PC11 while in the routine, but  
will change the internal flip-flop.  
Extended Memory Program  
Addressing (Beyond 2K)  
For programs of 2K words or less, the UPI-C42 ad-  
dresses program memory in the conventional man-  
ner. Addresses beyond 2047 can be reached by ex-  
ecuting a program memory bank switch instruction  
(SEL PMB0, SEL PMB1) followed by a branch in-  
struction (JMP or CALL). The bank switch feature  
extends the range of branch instructions beyond  
their normal 2K range and at the same time prevents  
the user from inadvertently crossing the 2K boundary.  
Hardware A20 Gate Support  
This feature has been provided to enhance the per-  
formance of the UPI-C42 when being used in a key-  
board controller application. The UPI-C42 design  
has included on chip logic to support a hardware  
GATEA20 feature which eliminates the need to pro-  
vide firmware to process A20 command sequences,  
6
 
UPI-C42/UPI-L42  
thereby providing additional user programmable  
memory space. This feature is enabled by the  
A20EN instruction and remains enabled until the de-  
vice is reset. It is important to note that the execu-  
tion of the A20EN instruction redefines Port 2, bit 1  
as a pure output pin with read only characteristics.  
The state of this pin can be modified only through a  
valid ‘‘D1’’ command sequence (see Table 1). Once  
enabled, the A20 logic will process a ‘‘D1’’ com-  
mand sequence (write to output port) by setting/re-  
setting the A20 bit on port 2, bit 1 (P2.1) without  
requiring service from the internal CPU. The host  
can directly control the status of the A20 bit. At no  
time during this host interface transaction will the  
IBF flag in the status register be activated. Table 1  
gives several possible GATEA20 command/data se-  
quences and UPI-C42 responses.  
SUSPEND  
The execution of the suspend instruction (82h or  
E2h) causes the UPI-C42 to enter the suspend  
mode. In this mode of operation the oscillator is not  
running and the internal CPU operation is stopped.  
The UPI-C42 consumes 40 mA in the suspend  
mode. This mode can only be exited by RESET.  
s
e
CPU operation will begin from PC  
UPI-C42 exits from the suspend power down mode.  
000h when the  
Suspend Mode Summary  
Oscillator Not Running  
#
CPU Operation Stopped  
#
E
Ports Tristated with Weak ( 210 mA) Pull-Up  
#
#
#
s
Micropower Mode (I  
40 mA)  
Table 1. D1 Command Sequences  
CC  
This mode is exited by RESET  
A0 R/W DB Pins IBF A20  
Comments  
(1)  
1
0
1
W
W
W
D1h  
DFh  
FFH  
0
0
0
n
Set A20 Sequence  
1
Only DB1 Is Processed  
(2)  
n
1
0
1
W
W
W
D1h  
DDh  
FFh  
0
0
0
n
0
n
Clear A20 Sequence  
1
1
0
1
W
W
W
W
D1h  
D1h  
DFh  
FFh  
0
0
0
0
n
n
1
n
Double Trigger Set  
Sequence  
1
1
0
W
W
W
D1h  
0
1
1
n
n
n
Invalid Sequence  
No Change in State  
of A20 Bit  
(3)  
XXh  
DDh  
NOTES:  
1. Indicates that P2.1 remains at the previous logic level.  
2. Only FFh commands in a valid A20 sequence have no  
effect on IBF. An FFh issued at any other time will activate  
IBF.  
3. Any command except D1.  
The above sequences assume that the GATEA20  
logic has been enabled via the A20EN instruction.  
As noted, only the value on DB 1 (data bus, bit 1) is  
processed. This bit will be directly passed through to  
P2.1 (port 2, bit 1).  
7
 
UPI-C42/UPI-L42  
Table 2 covers all suspend mode pin states. In addi-  
tion to the suspend power down mode, the UPI-C42  
will also support the NMOS power down mode as  
outlined in Chapter 4 of the UPI-42AH users manual.  
NEW UPI-C42 INSTRUCTIONS  
The UPI-C42 will support several new instructions to  
allow for the use of new C42 features. These in-  
structions are not necessary to the user who does  
not wish to take advantage of any new C42 function-  
ality. The C42 will be completely compatible with all  
current NMOS code/applications. In order to use  
new features, however, some code modifications will  
be necessary. All new instructions can easily be in-  
serted into existing code by use of the ASM-48 mac-  
ro facility as shown in the following example:  
Table 2. Suspend Mode Pin States  
Pins  
Suspend  
Ports 1 and 2  
Outputs  
Inputs  
Tristate  
Weak Pull-Up  
Disabled  
(1)  
DBB  
Macname MACRO  
DB 63H  
ENDM  
Outputs  
Inputs  
Normal  
Normal  
System Control  
Ý
Ý
CS , A0)  
Disabled  
Ý
,
(RD , WR  
New Instructions  
The following is a list of additions to the UPI-42 in-  
struction set. These instructions apply only to the  
UPI-C42. These instructions must be added to exist-  
ing code in order to use any new functionality.  
Ý
Reset  
Enabled  
Disabled  
Crystal Osc.  
(XTAL1, XTAL2)  
Test 0, Test 1  
Prog  
Disabled  
High  
SEL PMB0 Select Program Memory Bank 0  
OPCODE 0110 0011 (63h)  
Sync  
High  
PC Bit 11 is set to zero on next JMP or CALL instruc-  
tion. All references to program memory fall within  
the range of 02047 (07FFh).  
EA  
Disabled,  
No Pull-Up  
Ý
SS  
Disabled,  
Weak Pull-Up  
SEL PMB1 Select Program Memory Bank 1  
k
I
40 mA  
CC  
OPCODE 0111 0011 (73h)  
NOTES:  
1. DBB outputs are Tristate unless CS and RD are ac-  
PC Bit 11 is set to one on next JMP or CALL instruc-  
tion. All references to program memory fall within  
the range of 20484095 (800hFFFh).  
Ý
Ý
Ý
Ý
tive. DBB inputs are disabled unless CS and WR are  
active.  
2. A ‘‘disabled’’ input will not cause current to be drawn  
regardless of input level (within the supply range).  
3. Weak pull-ups have current capability of typically 5 mA.  
ENA20 Enables Auto A20 hardware  
OPCODE 0011 0011 (33h)  
Enables on chip logic to support Hardware A20 Gate  
feature. Will remain enabled until device is reset.  
8
 
UPI-C42/UPI-L42  
This circuitry gives the host direct control of port 2  
bit 1 (P2.1) without intervention by the internal CPU.  
When this opcode is executed, P2.1 becomes a ded-  
icated output pin. The status of this pin is read-able  
but can only be altered through a valid ‘‘D1’’ com-  
mand sequence (see Table 1).  
Pin  
XTAL 2  
Reset  
Test 0  
EA  
Function  
Clock Input  
Initialization and Address Latching  
Selection of Program or Verify Mode  
Activation of Program/Verify Signature  
Row/Security Bit Modes  
SUSPEND Invoke Suspend Power Down Mode  
OPCODE 1000 0010 (82h) or 1110 0010  
(E2h)  
BUS  
Address and Data Input  
Data Output During Verify  
Enables device to enter micro power mode. In this  
mode the external oscillator is off, CPU operation is  
stopped, and the Port pins are tristated. This mode  
can only be exited via a RESET signal.  
P
V
Address Input  
20–23  
Programming Power Supply  
Program Pulse Input  
DD  
PROG  
WARNING  
An attempt to program a missocketed UPI-C42 will result in  
severe damage to the part. An indication of a properly  
socketed part is the appearance of the SYNC clock output.  
The lack of this clock may be used to disable the program-  
mer.  
PROGRAMMING AND VERIFYING THE  
UPI-C42  
The UPI-C42 programming will differ from the NMOS  
device in three ways. First, the C42 will have a 4K  
user programmable array. The UPI-C42 will also be  
programmed using the Intel Quick-Pulse Program-  
ming Algorithm. Finally, port 2 bit three (P2.3) will be  
used during program as the extra address pin re-  
quired to program the upper 2K bank of additional  
memory. None of these differences have any effect  
on the full CHMOS to NMOS device compatibility.  
The extra memory is fully transparent to the user  
who does not need, or want, to use the extra memo-  
ry space of the UPI-C42.  
The Program/Verify sequence is:  
1. Insert 87C42 in programming socket  
e
e
e
0V, TEST 0  
e
5V, clock applied or inter-  
e
2. CS  
A
5V, V  
5V, V  
e
5V, RESET  
0V,  
CC  
DD  
0
e
nal oscillator operating, BUS floating, PROG  
5V.  
e
3. TEST 0  
0V (select program mode)  
e
4. EA  
12.75V (active program mode)  
e
5. V  
6. V  
6.25V (programming supply)  
12.75V (programming power)  
CC  
In brief, the programming process consists of: acti-  
vating the program mode, applying an address,  
latching the address, applying data, and applying a  
programming pulse. Each word is programmed com-  
pletely before moving on to the next and is followed  
by a verification step. The following is a list of the  
pins used for programming and a description of their  
functions:  
e
DD  
7. Address applied to BUS and P  
20–23  
e
8. RESET  
5V (latch address)  
9. Data applied to BUS  
e
10. PROG  
0V  
5V followed by one 100 ms pulse to  
e
11. TEST 0  
5V (verify mode)  
12. Read and verify data on BUS  
e
e
13. TEST 0  
14. RESET  
0V  
0V and repeat from step 6  
15. Programmer should be at conditions of step 1  
when the 87C42 is removed from socket  
Please follow the Quick-Pulse Programming flow  
chart for proper programming procedure shown in  
Figure 6.  
9
 
UPI-C42/UPI-L42  
flow chart of the Quick-Pulse Programming Algo-  
rithm is shown in Figure 6.  
The entire sequence of program pulses and byte  
e
verifications is performed at V  
6.25V and  
12.75V. When programming has been com-  
pleted, all bytes should be compared to the original  
CC  
e
V
DD  
e
e
data with V  
V
DD  
5V.  
CC  
A verify should be performed on the programmed  
bits to ensure that they have been correctly pro-  
e
e
grammed. The verify is performed with T0  
e
5V,  
5V,  
e
e
0V, and CS  
Ý
V
DD  
A0  
5V, EA  
12.75V, SS  
e
5V, PROG  
e
Ý
5V.  
In addition to the Quick-Pulse Programming Algo-  
rithm, the UPI-C42 OPT is also compatible with In-  
tel’s Int ligent Programming Algorithm which is used  
e
to program the NMOS UPI-42AH OTP devices.  
The entire sequence of program pulses and byte  
e
12.75V. When the int ligent Programming  
verifications is performed at V  
6.25V and  
CC  
e
cycle has been completed, all bytes should be com-  
V
DD  
e
e
e
pared to the original data with V  
5V.  
5.0, V  
DD  
CC  
Verify  
A verify should be performed on the programmed  
bits to determine that they have been correctly pro-  
e
e
grammed. The verify is performed with T0  
e
5V,  
5V,  
e
e
V
DD  
A0  
5V, EA  
0V, and CS  
12.75V, SS  
e
5V, PROG  
e
5V.  
SECURITY BIT  
The security bit is a single EPROM cell outside the  
EPROM array. The user can program this bit with the  
appropriate access code and the normal program-  
ming procedure, to inhibit any external access to the  
EPROM contents. Thus the user’s resident program  
is protected. There is no direct external access to  
this bit. However, the security byte in the signature  
row has the same address and can be used to  
check indirectly whether the security bit has been  
programmed or not. The security bit has no effect on  
the signature mode, so the security byte can always  
be examined.  
29041414  
Figure 6. Quick-Pulse Programming Algorithm  
Quick-Pulse Programming Algorithm  
As previously stated, the UPI-C42 will be pro-  
grammed using the Quick-Pulse Programming Algo-  
rithm, developed by Intel to substantially reduce the  
thorughput time in production programming.  
SECURITY BIT PROGRAMMING/  
VERIFICATION  
The Quick-Pulse Programming Algorithm uses initial  
pulses of 100 ms followed by a byte verification to  
determine when the address byte has been suc-  
cessfully programmed. Up to 25 100 ms pulses per  
byte are provided before a failure is recognized. A  
Programming  
a. Read the security byte of the signature mode.  
Make sure it is 00H.  
10  
 
UPI-C42/UPI-L42  
b. Apply access code to appropriate inputs to put  
the device into security mode.  
and will be present in the ROM and OTP ver-  
sions. Location 10H contains the manufacturer  
code. For Intel, it is 89H. Location 11H contains  
the device code.  
c. Apply high voltage to EA and V  
pins.  
DD  
d. Follow the programming procedure as per the  
Quick-Pulse Programming Algorithm with known  
data on the databus. Not only the security bit, but  
also the security byte of the signature row is pro-  
grammed.  
The code is 43H and 42H for the 8042AH/80C42  
and OTP 8742AH/87C42, respectively. The  
code is 44H for any device with the security bit  
set by Intel.  
C. User signatureÐThe user signature memory is  
implemented in the EPROM and consists of 2  
bytes for the customer to program his own signa-  
ture code (for identification purposes and quick  
sorting of previously programmed materials).  
e. Verify that the security byte of the signature  
mode contains the same data as appeared on  
e
the data bus. (If DB0DB7  
byte will contain FFH.)  
high, the security  
f. Read two consecutive known bytes from the  
EPROM array and verify that the wrong data are  
retrieved in at least one verification. If the  
EPROM can still be read, the security bit may  
have not been fully programmed though the se-  
curity byte in the signature mode has.  
D. Test signatureÐThis memory is used to store  
testing information such as: test data, bin num-  
ber, etc. (for use in quality and manufacturing  
control).  
E. Security byteÐThis byte is used to check  
whether the security bit has been programmed  
(see the security bit section).  
Verification  
F. UPI-C42 Intel SignatureÐApplies only to  
CHMOS device. Location 20H contains the man-  
ufacturer code and location 21H contains the de-  
vice code. The Intel UPI-C42 manufacturer’s  
code is 99H. The device ID’s are 82H for the  
OTP version and 83H for the ROM version. The  
device ID’s are the same for the UPI-L42.  
Since the security bit address overlaps the address  
of the security byte of the signature mode, it can be  
used to check indirectly whether the security bit has  
been programmed or not. Therefore, the security bit  
verification is a mere read operation of the security  
e
security bit unprogrammed). Note  
byte of the signature row (0FFH  
e
security bit pro-  
grammed; 00H  
The signature mode can be accessed by setting  
e
that during the security bit programming, the reading  
of the security byte does not necessarily indicate  
that the security bit has been successfully pro-  
grammed. Thus, it is recommended that two consec-  
utive known bytes in the EPROM array be read and  
the wrong data should be read at least once, be-  
cause it is highly improbable that random data coin-  
cides with the correct ones twice.  
e
P10  
0, P11P17  
1, and then following the pro-  
gramming and/or verification procedures. The loca-  
tion of the various address partitions are as shown in  
Table 3.  
SYNC MODE  
The Sync Mode is provided to ease the design of  
multiple controller circuits by allowing the designer  
to force the device into known phase and state time.  
The Sync Mode may also be utilized by automatic  
test equipment (ATE) for quick, easy, and efficient  
synchronizing between the tester and the DUT (de-  
vice under test).  
SIGNATURE MODE  
The UPI-C42 has an additional 64 bytes of EPROM  
available for Intel and user signatures and miscella-  
neous purposes. The 64 bytes are partitioned as fol-  
lows:  
A. Test code/checksumÐThis can accommodate  
up to 25 bytes of code for testing the internal  
nodes that are not testable by executing from the  
external memory. The test code/checksum is  
present on ROMs, and OTPs.  
Sync Mode is enabled when SS pin is raised to high  
a
voltage level of  
12 volts. To begin synchroniza-  
tion, T0 is raised to 5 volts at least four clock cycles  
after SS. T0 must be high for at least four X2 clock  
cycles to fully reset the prescaler and time state  
generators. T0 may then be brought down during  
low state of X2. Two clock cycles later, with the ris-  
ing edge of X2, the device enters into Time State 1,  
Phase 1. SS is then brought down to 5 volts 4 clocks  
later after T0. RESET is allowed to go high 5 tCY (75  
clocks) later for normal execution of code.  
B. Intel signatureÐThis allows the programmer to  
read from the UPI-41AH/42AH/C42 the manu-  
facturer of the device and the exact product  
name. It facilitates automatic device identification  
11  
 
UPI-C42/UPI-L42  
Table 3. Signature Mode Table  
Address  
Device  
Type  
No. of  
Bytes  
Test Code/Checksum  
0
16H  
0FH  
ROM/OTP  
25  
1EH  
11H  
13H  
15H  
Intel Signature  
10H  
12H  
14H  
ROM/OTP  
OTP  
2
2
User Signature  
Test Signature  
ROM/OTP  
ROM/OTP  
ROM/OTP  
ROM/OTP  
2
Security Byte  
1FH or 3FH  
2
UPI-C42 Intel Signature  
User Defined UPI-C42 OTP EPROM Space  
20H  
22H  
21H  
3EH  
2
30  
ACCESS CODE  
The following table summarizes the access codes required to invoke the Sync Mode, Signature Mode,  
and the Security Bit, respectively. Also, the programming and verification modes are included for  
comparison.  
Access Code  
Control Signals  
Data Bus  
Modes  
Port 2  
Port 1  
T0 RST SS EA PROG  
V
DD  
V
CC  
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6 7  
Programming  
Mode  
0
0
0
1
0
1
0
1
0
1
1
HV  
1
V
V
V
DDH CC  
Address  
Data In  
Addr  
Addr  
Addr  
Addr  
a
a
X
X
X
X X X  
0
1
HV STB  
V
DDH CC  
Verification  
Mode  
1
HV  
HV  
0
1
1
X
V
V
CC  
V
CC  
V
CC  
Address  
Data Out  
a
0
a
1
X
X
X
X X X  
CC  
CC  
CC  
1
V
V
Sync Mode  
STB  
High  
HV  
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
1
X
1
X X X  
X X 1  
Signature Prog  
Mode  
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
HV  
1
V
V
V
DDH CC  
Addr. (see Sig Mode Table)  
Data In  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
HV STB  
V
DDH CC  
Verify  
HV  
HV  
HV  
1
1
1
V
V
Addr. (see Sig Mode Table)  
Data Out  
CC  
CC  
CC  
CC  
V
V
Security Prog  
Bit/Byte  
V
V
V
DDH CC  
Address  
HV STB  
V
DDH CC  
Data In  
Verify  
HV  
HV  
1
1
V
V
Address  
CC  
CC  
CC  
CC  
V
V
Data Out  
NOTE:  
1. a  
e
e
e
0 or 1; a  
0 or 1. a must  
0
a .  
1
0
1
12  
 
UPI-C42/UPI-L42  
SYNC MODE TIMING DIAGRAMS  
29041415  
Minimum Specifications  
SYNC Operation Time, t  
e
e
3.5 XTAL 2 Clock cycles. Reset Time, t  
4 t  
.
CY  
SYNC  
RS  
NOTE:  
The rising and falling edges of T0 should occur during low state of XTAL 2 clock.  
APPLICATIONS  
29041412  
Figure 7. UPI-C42 Keyboard Controller  
290414–9  
Figure 8. 8088-UPI-C42 Interface  
13  
 
UPI-C42/UPI-L42  
APPLICATIONS (Continued)  
29041410  
Figure 9. 8048H-UPI-C42 Interface  
29041411  
Figure 10. UPI-C42-8243 Keyboard Scanner  
29041413  
Figure 11. UPI-C42 80-Column Matrix Printer Interface  
14  
 
UPI-C42/UPI-L42  
ABSOLUTE MAXIMUM RATINGS*  
NOTICE: This is a production data sheet. The specifi-  
cations are subject to change without notice.  
a
Ambient Temperature Under Bias ÀÀÀÀ0 C to 70 C  
§
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 C to 150 C  
§
§
*WARNING: Stressing the device beyond the ‘‘Absolute  
Maximum Ratings’’ may cause permanent damage.  
These are stress ratings only. Operation beyond the  
‘‘Operating Conditions’’ is not recommended and ex-  
tended exposure beyond the ‘‘Operating Conditions’’  
may affect device reliability.  
b
a
§
Voltage on Any Pin with  
Respect to GroundÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 0.5V to 7V  
b
a
Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5 W  
e
a
0 C to 70 C, V  
e
e a  
a
5V 10%; 3.3V 10% UPI-L42  
g
g
DC CHARACTERISTICS T  
V
DD  
§
§
UPI-C42  
A
CC  
UPI-L42  
Max  
Symbol  
Parameter  
Units  
Notes  
Min Max Min  
b
b
a
0.8  
V
V
Input Low Voltage  
0.5 0.8  
0.3  
V
V
All Pins  
IL  
a
Input High Voltage  
(Except XTAL2, RESET)  
2.0  
V
2.0  
V
V
0.3  
IH  
CC  
CC  
a
V
V
V
V
V
V
Input High Voltage  
(XTAL2, RESET)  
3.5  
V
2.0  
0.3  
V
V
V
V
V
IH1  
OL  
CC  
CC  
e
e
Output Low Voltage (D D )  
0
0.45  
0.45  
0.45  
0.45  
0.45  
0.45  
I
I
2.0 mA UPI-C42  
1.3 mA UPI-L42  
7
OL  
OL  
e
e
Output Low Voltage  
(P , P , Sync)  
I
I
1.6 mA UPI-C42  
1 mA UPI-L42  
OL1  
OL2  
OH  
OL  
P
P
10 17 20 27  
OL  
e
e
Output Low Voltage (PROG)  
I
I
1.0 mA UPI-C42  
0.7 mA UPI-L42  
OL  
OL  
e b  
e b  
Output High Voltage (D D ) 2.4  
0
2.4  
2.4  
I
I
400 mA UPI-C42  
260 mA UPI-L42  
7
OH  
OH  
e b  
e b  
Output High Voltage  
(All Other Outputs)  
2.4  
I
I
50 mA UPI-C42  
25 mA UPI-L42  
OH1  
OH  
OH  
s
s
g
g
g
g
I
I
I
Input Leakage Current  
(T , T , RD, WR, CS, A , EA)  
10  
10  
10  
10  
mA  
mA  
V
V
V
CC  
IL  
SS  
SS  
IN  
0
1
0
s
s
a
Output Leakage Current  
(D D , High Z State)  
V
0.45  
V
V
CC  
OFL  
LI  
OUT  
0
7
b
b
b
b
175  
Low Input Load Current  
(P , P  
50  
250  
35  
mA Port Pins  
e
P
10 17 20 27  
P
)
Min V  
Max V  
2.4V  
0.45V  
IN  
e
IN  
s
b
b
40  
I
I
I
Low Input Load Current  
(RESET, SS)  
40  
mA  
V
V
IL  
LI1  
HI  
IN  
e
Port Sink Current  
(P  
V
V
3.0V  
5.0V  
CC  
5.0  
2.5  
mA  
mA  
e
P
10 17 20 27  
, P  
P
)
IH  
V
Supply Current  
DD  
4
DD  
15  
 
UPI-C42/UPI-L42  
DC CHARACTERISTICS  
e
a
0 C to 70 C, V  
e
e a  
a
5V 10%; 3.3V 10% UPI-L42 (Continued)  
g
g
T
A
V
§
§
CC  
DD  
UPI-C42  
Min Max  
UPI-L42  
Min Max  
Symbol  
Parameter  
Units  
Notes  
a
I
I
Total Supply Current:  
@
Active Mode 12.5 MHz  
CC  
DD  
30  
20  
mA  
Typical 14 mA UPI-C42,  
9 mA UPI-L42  
(1, 4)  
Osc. Off  
Suspend Mode  
40  
5
26  
mA  
I
I
Standby Power Down  
Supply Current  
3.5  
mA  
NMOS Compatible  
Power Down Mode  
DD  
IH  
e
Input Leakage Current  
(P P , P –P  
100  
100  
mA  
V
IN  
V
CC  
)
27  
10  
17 20  
(1)  
(1)  
e
C
C
Input Capacitance  
I/O Capacitance  
10  
20  
10  
20  
pF  
pF  
T
25 C  
§
25 C  
§
IN  
A
A
e
T
IO  
NOTE:  
1. Sampled, not 100% tested.  
DC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42)  
e
e
e
g
25 C 5 C, V  
g
6.25V 0.25V, V  
g
12.75V 0.25V  
T
A
§
§
CC  
DD  
Symbol  
Parameter  
Min  
12.5  
4.75  
2.0  
Max  
13  
Units  
(1)  
V
V
V
V
V
V
V
V
Program Voltage High Level  
Voltage Low Level  
DDH  
DDL  
PH  
DD  
V
DD  
5.25  
5.5  
V
V
V
PROG Program Voltage High Level  
PROG Voltage Low Level  
Input High Voltage for EA  
EA Voltage Low Level  
b
0.5  
0.8  
PL  
(2)  
V
12.0  
13.0  
5.25  
50.0  
1.0  
EAH  
EAL  
b
0.5  
V
I
I
V
DD  
High Voltage Supply Current  
mA  
DD  
EA  
(4)  
EA High Voltage Supply Current  
mA  
NOTES:  
1. Voltages over 13V applied to pin V  
will permanently damage the device.  
DD  
must be applied to EA before V  
must be applied simultaneously or before V  
2. V  
3. V  
and removed after V  
.
EAH  
DDH  
DDL  
and must be removed simultaneously or after V .  
DD  
CC  
DD  
4. Sampled, not 100% tested.  
16  
 
UPI-C42/UPI-L42  
AC CHARACTERISTICS  
e
a
0 C to 70 C, V  
e
e
e a  
a
5V 10%; 3.3V 10% for the UPI-L42  
g
g
T
A
0V, V  
V
DD  
§
§
SS  
CC  
NOTE:  
All AC Characteristics apply to both the UPI-C42 and UPI-L42  
DBB READ  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
t
CS, A Setup to RD  
0
v
u
AR  
t
CS, A Hold After RD  
0
0
ns  
RA  
t
t
t
t
RD Pulse Width  
160  
ns  
RR  
AD  
RD  
DF  
CS, A to Data Out Delay  
0
130  
130  
85  
ns  
RD to Data Out Delay  
v
RD to Data Float Delay  
u
0
ns  
ns  
DBB WRITE  
Symbol  
Parameter  
Min  
0
Max  
Units  
ns  
t
CS, A Setup to WR  
0
v
u
AW  
t
CS, A Hold After WR  
0
0
ns  
WA  
t
t
t
WR Pulse Width  
160  
130  
0
ns  
WW  
DW  
WD  
Data Setup to WR  
ns  
u
u
Data Hold After WR  
ns  
17  
 
UPI-C42/UPI-L42  
AC CHARACTERISTICS  
e
a
0 C to 70 C, V  
e
e
e a  
a
5V 10%; 3.3V 10% for the UPI-L42 (Continued)  
g
g
T
A
0V, V  
V
DD  
§
§
SS  
CC  
CLOCK  
Symbol  
Parameter  
Min  
1.2  
80  
Max  
9.20  
613  
Units  
(1)  
ms  
t
t
t
t
t
t
UPI-C42/UPI-L42  
Cycle Time  
CY  
UPI-C42/UPI-L42  
Clock Period  
ns  
ns  
ns  
ns  
ns  
CYC  
PWH  
PWL  
R
Clock High Time  
Clock Low Time  
Clock Rise Time  
Clock Fall Time  
30  
30  
10  
10  
F
NOTE:  
1. t  
e
15/f(XTAL)  
CY  
AC CHARACTERISTICS DMA  
Symbol  
Parameter  
DACK to WR or RD  
Min  
Max  
Units  
ns  
t
t
t
t
0
0
0
ACC  
CAC  
ACD  
CRQ  
RD or WR to DACK  
ns  
DACK to Data Valid  
130  
110  
ns  
(1)  
ns  
RD or WR to DRQ Cleared  
NOTE:  
1. C  
e
150 pF.  
L
AC CHARACTERISTICS PORT 2  
(3)  
f(t )  
CY  
Symbol  
Parameter  
Min  
Max  
Units  
(1)  
(2)  
(1)  
(2)  
(1)  
(2)  
b
t
t
t
t
t
t
t
Port Control Setup Before Falling Edge of PROG  
Port Control Hold After Falling Edge of PROG  
PROG to Time P2 Input Must Be Valid  
Input Data Hold Time  
1/15 t  
28  
55  
ns  
ns  
ns  
ns  
ns  
ns  
CP  
PC  
PR  
PF  
DP  
PD  
PP  
CY  
1/10 t  
125  
CY  
b
8/15 t  
16  
650  
150  
CY  
0
Output Data Setup Time  
2/10 t  
250  
45  
CY  
b
80  
Output Data Hold Time  
1/10 t  
CY  
PROG Pulse Width  
6/10 t  
750  
ns  
CY  
NOTES:  
e
e
e
1. C  
2. C  
80 pF.  
20 pF.  
1.25 ms.  
L
L
3. t  
CY  
18  
 
UPI-C42/UPI-L42  
AC CHARACTERISTICSÐPROGRAMMING (UPI-C42 AND UPI-L42)  
e
e
e a  
e
g
25 C 5 C, V  
g
6.25V 0.25V, V  
g
5V 0.25V, V  
g
12.75V 0.25V  
T
A
§
§
CC  
DDL  
DDH  
(87C42/87L42 ONLY)  
Symbol  
Parameter  
Address Setup Time to RESET  
Min  
Max  
Units  
t
4t  
u
u
AW  
CY  
t
Address Hold Time after RESET  
4t  
WA  
CY  
t
Data in Setup Time to PROG  
4t  
v
u
DW  
CY  
t
Data in Hold Time after PROG  
4t  
WD  
CY  
t
t
t
t
t
Initial Program Pulse Width  
95  
105  
ms  
PW  
TW  
WT  
DO  
WW  
Test 0 Setup Time for Program Mode  
Test 0 Hold Time after Program Mode  
Test 0 to Data Out Delay  
4t  
4t  
CY  
CY  
4t  
CY  
RESET Pulse Width to Latch Address  
PROG Rise and Fall Times  
4t  
CY  
t , t  
r
0.5  
2.5  
4t  
100  
ms  
ms  
f
t
t
t
t
CPU Operation Cycle Time  
3.75  
CY  
RESET Setup Time before EA  
u
RE  
CY  
(1)  
Overprogram Pulse Width  
2.85  
1t  
78.75  
ms  
OPW  
DE  
EA High to V High  
DD  
CY  
NOTES:  
1. This variation is a function of the iteration counter value, X.  
2. If TEST 0 is high, t can be triggered by RESET  
.
u
DO  
AC TESTING INPUT/OUTPUT WAVEFORM  
AC TESTING LOAD CIRCUIT  
INPUT/OUTPUT  
29041416  
29041417  
19  
 
UPI-C42/UPI-L42  
DRIVING FROM AN EXTERNAL SOURCE  
29041418  
29041419  
Rise and Fall Times Should Not  
Exceed 10 ns. Resistors to V  
NOTE:  
See XTAL1 Configuration Table.  
CC  
3.5V  
e
are Needed to Ensure V  
if TTL Circuitry is Used.  
IH  
LC OSCILLATOR MODE  
CRYSTAL OSCILLATOR MODE  
L
C
NOMINAL  
1
e
f
45 H 20 pF 5.2 MHz  
120 H 20 pF 3.2 MHz  
2q LC  
Ê
0
a
C
3Cpp  
e
C
Ê
2
29041421  
C1 5 pF (STRAY 5 pF)  
a
j
Pin-to-Pin Capacitance  
Cpp  
5–10 pF  
C2 (CRYSTAL  
STRAY) 8 pF  
C3 2030 pF INCLUDING STRAY  
Crystal Series Resistance Should  
be Less Than 30X at 12.5 MHz.  
29041420  
Each C Should be Approximately 20 pF, including Stray Capacitance.  
XTAL1 Configuration Table  
XTAL1 Connection  
2) 10 KX Resistor  
to Ground  
1) to Ground  
3) Not Connected  
Not recommended for CHMOS  
designs. Causes approximately  
16 mA of additional current flow  
through the XTAL1 pin on UPI-  
C42 and approximately 11 mA of  
additional current through XTAL1  
on the UPI-L42.  
Recommended configuration for  
designs which will use both  
NMOS and CHMOS parts. This  
configuration limits the additional  
current through the XTAL1 pin to  
approximately 1 mA, while  
maintaining compatibility with the  
NMOS device.  
Low power configuration  
recommended for CHMOS only  
designs to provide lowest  
possible power consumption.  
This configuration will not work  
with the NMOS device.  
20  
 
UPI-C42/UPI-L42  
WAVEFORMS  
READ OPERATIONÐDATA BUS BUFFER REGISTER  
29041422  
WRITE OPERATIONÐDATA BUS BUFFER REGISTER  
29041423  
CLOCK TIMING  
29041424  
21  
 
UPI-C42/UPI-L42  
WAVEFORMS (Continued)  
COMBINATION PROGRAM/VERIFY MODE  
29041425  
NOTES:  
1. A must be held low (0V) during program/verify modes.  
0
2. For V , V , V , V , V  
, and V  
, please consult the D.C. Characteristics Table.  
DDL  
IH IH1 IL IL1 DDH  
3. When programming the 87C42, a 0.1 mF capacitor is required across V  
transients which can damage the device.  
and ground to suppress spurious voltage  
DD  
VERIFY MODE  
29041426  
NOTES:  
1. PROG must float if EA is low.  
e
2. PROG must float or  
5V when EA is high.  
e
e
3. P P  
10  
4. P P  
24  
5V or must float.  
5V or must float.  
17  
27  
5. A must be held low during programming/verify modes.  
0
22  
 
UPI-C42/UPI-L42  
WAVEFORMS (Continued)  
DMA  
29041427  
PORT 2  
29041428  
PORT TIMING DURING EXTERNAL ACCESS (EA)  
29041429  
On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync  
the Program Counter Contents are Available.  
23  
 
UPI-C42/UPI-L42  
Table 4. UPI Instruction Set  
Mnemonic  
Description  
Bytes Cycles  
Mnemonic  
Description  
Bytes Cycles  
ACCUMULATOR  
DATA MOVES  
ADD A, Rr  
@
ADD A, Rr  
Add register to A  
Add data memory  
to A  
1
1
1
1
MOV A, Rr  
@
MOV A, Rr  
Move register to A  
Move data memory  
to A  
1
1
1
1
Ý
ADD A, data  
Ý
MOV A, data Move immediate to A  
Add immediate to A  
Add register to A  
with carry  
2
1
2
1
2
1
1
2
1
1
ADDC A, Rr  
MOV Rr, A  
@
MOV Rr, A  
Move A to register  
Move A to data  
memory  
@
ADDC A, Rr  
Add data memory  
to A with carry  
1
2
1
2
Ý
MOV Rr, data Move immediate to  
2
2
2
2
Ý
ADDC A, data Add immediate  
register  
@
MOV Rr,  
to A with carry  
Move immediate to  
data memory  
Move PSW to A  
Move A to PSW  
Exchange A and  
register  
Ý
data  
ANL A, Rr  
@
ANL, A Rr  
AND register to A  
AND data memory  
to A  
1
1
1
1
MOV A, PSW  
MOV PSW, A  
XCH A, Rr  
1
1
1
1
1
1
Ý
ANL A, data  
AND immediate to A  
OR register to A  
OR data memory  
to A  
2
1
1
2
1
1
ORL A, Rr  
@
ORL, A, Rr  
@
XCH A, Rr  
Exchange A and  
data memory  
Exchange digit of A  
and register  
1
1
1
1
1
1
2
2
@
XCHD A, Rr  
Ý
ORL A, data  
OR immediate to A  
Exclusive OR regis-  
ter to A  
2
1
2
1
XRL A, Rr  
@
MOVP A,  
A
Move to A from  
current page  
@
XRL A, Rr  
Exclusive OR data  
memory to A  
1
2
1
2
@
MOVP3, A,  
A
Move to A from  
page 3  
Ý
XRL A, data  
Exclusive OR imme-  
diate to A  
TIMER/COUNTER  
INC A  
DEC A  
CLR A  
CPL A  
DA A  
Increment A  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MOV A, T  
MOV T, A  
STRT T  
Read Timer/Counter  
1
1
1
1
1
1
1
1
1
1
1
1
Decrement A  
Clear A  
Load Timer/Counter  
Start Timer  
Complement A  
Decimal Adjust A  
Swap nibbles of A  
Rotate A left  
STRT CNT  
STOP TCNT  
EN TCNTI  
Start Counter  
Stop Timer/Counter  
Enable Timer/  
SWAP A  
RL A  
Counter Interrupt  
Disable Timer/  
Counter Interrupt  
RLC A  
Rotate A left through  
carry  
DIS TCNTI  
1
1
RR A  
Rotate A right  
Rotate A right  
through carry  
1
1
1
1
CONTROL  
*EN A20  
EN DMA  
RRC A  
Enable A20 Logic  
Enable DMA Hand-  
shake Lines  
1
1
1
1
INPUT/OUTPUT  
IN A, Pp  
Input port to A  
1
1
2
2
2
2
EN I  
Enable IBF Interrupt  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OUTL Pp, A  
Ý
Output A to port  
ANL Pp, data AND immediate to  
port  
DIS I  
Diable IBF Inter-  
rupt  
Ý
ORL Pp, data OR immediate to  
2
1
1
1
1
1
1
1
2
1
1
1
2
2
2
2
EN FLAGS  
*SEL PMB0  
*SEL PMB1  
SEL RB0  
SEL RB1  
Enable Master  
Interrupts  
port  
IN A, DBB  
Input DBB to A,  
clear IBF  
Select Program  
memory bank 0  
Select Program  
memory bank 1  
Select register  
bank 0  
OUT DBB, A  
MOV STS, A  
MOVD A, Pp  
MOVD Pp, A  
ANLD Pp, A  
ORLD Pp, A  
Output A to DBB,  
set OBF  
A A to Bits 4–7 of  
4
Status  
7
Input Expander  
port to A  
Select register  
bank 1  
Output A to  
Expander port  
AND A to Expander  
port  
* UPI-C42/UPI-L42 Only.  
OR A to Expander  
port  
24  
 
UPI-C42/UPI-L42  
Table 4. UPI Instruction Set (Continued)  
Mnemonic  
Description  
Bytes Cycles  
Mnemonic  
Description  
Bytes Cycles  
CONTROL (Continued)  
*SUSPEND Invoke Suspend Power-  
down mode  
BRANCH  
1
1
2
1
JMP addr  
@
Jump unconditional  
Jump indirect  
2
1
2
2
2
2
JMPP  
A
NOP  
No Operation  
DJNZ Rr, addr Decrement register  
and jump  
REGISTERS  
e
e
JC addr  
Jump on Carry  
Jump on Carry  
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
INC Rr  
@
INC Rr  
Increment register  
Increment data  
memory  
1
1
1
1
JNC addr  
JZ addr  
Jump on A Zero  
Jump on A not Zero  
JNZ addr  
JT0 addr  
JNT0 addr  
JT1 addr  
JNT1 addr  
JF0 addr  
JF1 addr  
JTF addr  
DEC Rr  
Decrement register  
1
1
e
e
e
e
Jump on T0  
Jump on T0  
Jump on T1  
Jump on T1  
1
0
1
0
SUBROUTINE  
CALL addr  
RET  
Jump to subroutine  
Return  
2
1
1
2
2
2
RETR  
Return and restore  
status  
e
e
Jump on F0 Flag  
Jump on F1 Flag  
1
1
FLAGS  
CLR C  
Jump on Timer Flag  
e
Clear Carry  
1
1
1
1
1
1
1
1
1
1
1
1
1, Clear Flag  
Jump on IBF Flag  
CPL C  
Complement Carry  
Clear Flag 0  
JNIBF addr  
JOBF addr  
JBb addr  
2
2
2
2
2
2
e
Jump on OBF Flag  
CLR F0  
CPL F0  
CLR F1  
CPL F1  
0
Complement Flag 0  
Clear F1 Flag  
e
1
Complement F1 Flag  
Jump on Accumula-  
for Bit  
*UPI-C42/UPI-L42 Only.  
REVISION SUMMARY  
The following has been changed since Revision  
-003:  
1. Delete all references to standby power down  
mode.  
The following has been changed since Revision  
-002:  
1. Added information on keyboard controller prod-  
uct family.  
2. Added I specification for the UPI-L42.  
HI  
The following has been changed since Revision  
-001:  
1. Added UPI-L42 references and specification.  
25  
 

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