NuDAQ® / NuIPC®
PCI-7200 / cPCI-7200 / LPCI-7200S
12MB/S High Speed
Digital Input/ Output Card
User’s Guide
Recycled Paper
©Copyright 2003 ADLINK Technology Inc.
All Rights Reserved.
Manual Rev. 2.30: October 13, 2003
Part No: 50-11102-101
The information in this document is subject to change without prior notice in
order to improve reliability, design, and function and does not represent a
commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, special, incidental,
or consequential damages arising out of the use or inability to use the product
or documentation, even if advised of the possibility of such damages.
This document contains proprietary information protected by copyright. All
rights are reserved. No part of this manual may be reproduced by any
mechanical, electronic, or other means in any form without prior written
permission of the manufacturer.
Trademarks
NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK Technology
Inc.
Other product names mentioned herein are used for identification purposes
only and may be trademarks and/or registered trademarks of their respective
companies.
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need any help or service, please contact us.
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Table of Contents
Chapter 1 Introduction.........................................1
1.1 Applications......................................................................... 1
1.2 Features ............................................................................... 2
1.3 Specifications...................................................................... 2
1.4 Software Supporting........................................................... 4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
Programming Library .......................................................... 4
PCIS-LVIEW: LabVIEW® Driver ........................................... 5
PCIS-VEE: HP-VEE Driver ................................................... 5
DAQBenchTM: ActiveX Controls ......................................... 5
DASYLabTM PRO .................................................................. 5
PCIS-DDE: DDE Server and InTouchTM ............................. 5
PCIS-ISG: ISaGRAFTM driver............................................... 6
PCIS-ICL: InControlTM Driver............................................... 6
PCIS-OPC: OPC Server ........................................................ 6
Chapter 2 Installation ..........................................7
2.1 What Included ....................................................................... 7
2.2 Unpacking ............................................................................. 8
2.3 Device Installation for Windows Systems ............................. 8
2.4 PCI-7200/cPCI-7200/LPCI-7200S’s Layout.......................... 9
2.5 Hardware Installation Outline.............................................. 13
2.6 Connector Pin Assignments................................................ 14
2.6.1
2.6.2
2.6.3
PCI-7200 Pin Assignments.................................................. 14
cPCI-7200 Pin Assignments ................................................ 16
LPCI-7200S Pin Assignments.............................................. 17
2.7 8254 for Timer Pacer Generation........................................ 19
2.8 LPCI-7200S PCI Bus Signaling........................................... 20
2.9 Onboard Pull-ups and Terminations in digital input............ 20
Chapter 3 Register Format.................................21
3.1 I/O Registers Format........................................................... 21
3.2 Digital Input Register (BASE + 10)...................................... 22
3.3 Digital Output Register (BASE + 14)................................... 22
3.4 DIO Status & Control Register (BASE + 18)....................... 22
3.5 Interrupt Status & Control Register (BASE + 1C) ............... 24
3.6 8254 Timer Registers (BASE + 0)....................................... 27
Chapter 4 Operation Theory...............................29
4.1 Direct Program Control ....................................................... 29
4.2 Timer Pacer Mode............................................................... 30
Table of Contents
i
•
4.3 External Clock Mode........................................................... 31
4.4 Handshaking ....................................................................... 31
4.5 Timing Characteristic .......................................................... 33
Chapter 5 C/C++ Libraries..................................37
5.1 Libraries Installation ............................................................ 37
5.2 Programming Guide............................................................ 38
5.2.1
5.2.2
Naming Convention ............................................................. 38
Data Types .......................................................................... 38
5.3 _7200_Initial........................................................................ 39
5.4 _7200_Switch_Card_No ..................................................... 40
5.5 _7200_AUX_DI ................................................................... 40
5.6 _7200_AUX_DI_Channel.................................................... 41
5.7 _7200_AUX_DO.................................................................. 41
5.8 _7200_AUX_DO_Channel.................................................. 42
5.9 _7200_DI............................................................................. 42
5.10 _7200_DI_Channel ............................................................. 43
5.11 _7200_DO........................................................................... 43
5.12 _7200_DO_Channel ........................................................... 44
5.13 _7200_Alloc_DMA_Mem .................................................... 45
5.14 _7200_Free_DMA_Mem..................................................... 46
5.15 _7200_Alloc_DBDMA_Mem ............................................... 46
5.16 _7200_Free_DBDMA_Mem................................................ 47
5.17 _7200_DI_DMA_Start......................................................... 47
5.18 _7200_DI_DMA_Status ...................................................... 50
5.19 _7200_DI_DMA_Stop ......................................................... 51
5.20 _7200_DblBufferMode ........................................................ 51
5.21 _7200_CheckHalfReady ..................................................... 52
5.22 _7200_DblBufferTransfer.................................................... 52
5.23 _7200_GetOverrunStatus ................................................... 53
5.24 _7200_DO_DMA_Start ....................................................... 53
5.25 _7200_DO_DMA_Status..................................................... 54
5.26 _7200_DO_DMA_Stop ....................................................... 55
5.27 _7200_DI_Timer.................................................................. 56
5.28 _7200_DO_Timer................................................................ 57
Chapter 6 Double Buffer Mode Principle ...........59
Chapter 7 Limitations ........................................61
Warranty.............................................................63
Table of Contents ii
•
How to Use This Guide
This manual is designed to help users use the PCI-7200, cPCI-7200, and
LPCI-7200S. The functionality of PCI-7200, cPCI-7200, and LPCI-7200S are
the same except that the cPCI-7200 has 4 auxiliary digital inputs and outputs.
In this guide, “PCI-7200” represents PCI-7200, cPCI-7200, and LPCI-7200S if
not specified.
The manual describes how to modify various settings on the PCI-7200 card to
meet application requirements. It is divided into seven chapters:
Chapter 1
Chapter 2
Introduction
Gives an overview of product features, applications, and
specifications.
Installation
Describes how to install the PCI-7200. The layout of PCI-7200 is
shown, and the installation procedures, pin assignment of
connectors, and timer pacer generation are specified.
Chapter 3
Register Structure & Format
Describes the low-level register structure and format of the
PCI-7200.
Chapter 4
Chapter 5
Operation Theory
Describes how the PCI-7200 works.
C/C++ & DLL Libraries
Describes the high level C and DLL libraries to assist with
programming in DOS and Windows environments.
Chapter 6
Chapter 7
Double Buffer Mode Principle
Describes the data buffer for double-buffered DMA DI
operations.
Limitations
Describes three limitations on using PCI-7200.
1
Introduction
The PCI-7200, cPCI-7200, and LPCI-7200S are PCI/CompactPCI/Low profile
PCI form factor high-speed digital I/O cards, consisting of 32 digital input
channels, and 32 digital output channels. High performance design and
state-of-the-art technology make this card suitable for high-speed digital input
and output applications.
The PCI-7200 performs high-speed data transfers using bus-mastering DMA
via the 32-bit PCI bus architecture. The maximum data transfer rates can be
up to 12MB per second—very suitable for interfacing high-speed peripherals
and your computer system.
Several different digital I/O operation modes are supported:
1. Direct Program Control: the digital inputs and outputs can be accessed
and controlled by its corresponding I/O ports directly.
2. Timer Pacer Mode: the digital input and output operations are handled by
internal timer pacer clock and transferred by bus mastering DMA.
3. External Clock Mode: the digital input operations are handled by an
external input strobe signal (I_REQ) and transferred by bus mastering DMA.
4. Handshaking: through the REQ and ACK signals, digital I/O data can utilize
simple handshaking data transfer.
1.1 Applications
‹
‹
‹
‹
‹
‹
‹
Interface to high-speed peripherals
High-speed data transfers from other computers
Digital I/O control
Interface to external high-speed A/D and D/A converter
Digital pattern generator
Waveform and pulse generation
BCD interface driver
Introduction
1
•
1.2 Features
The PCI-7200 high-speed DIO Card provides the following advanced features:
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
32 TTL digital input channels
32 TTL digital output channels
Transfer up to 12M Bytes per second
High output driving and low input loading
32-bit PCI bus, Plug and Play
On-board internal timer pacer clock
Internal timer controls input sampling rate
Internal timer controls digital output rate
ACK and REQ for handshaking
On-board 32-byte FIFO for both digital input and output
Extra 2k double word digital input FIFO for cPCI-7200
4 auxiliary digital input and output channels (cPCI-7200 only)
Diode terminators for 32 input channels and control
signals(cPCI-7200/LPCI-7200S)
‹
Multiple interrupt sources are selectable by software
1.3 Specifications
‹
Digital I/O (DIO)
z Number of DI Channels: 32 TTL compatible
z Number of DO Channels: 32 TTL compatible
z Data Transfer Mode
♦ Program I/O
♦ Internal timer pacer transfer
♦ External I_REG strobe input
♦ Handshake data transfer
z Maximum Transfer Speed:
♦ 3MHz (12MHz) by external clock, handshake or external strobe
♦ 2MHz (8MHz) by internal timer pacer transfer
z FIFO:
z 8 words (32-bit) (for PCI-7200/LPCI-7200S)
2k + 8 words (32-bit) (for cPCI-7200 Digital input channels)
2
Introduction
•
z Input Voltage:
Low: Min. 0V; Max. 0.8V
High: Min. +2.0V
z Input Load:
Low: +0.5V @ -0.6mA max.
High: +2.7V @ +20µA max.
z Output Voltage:
Low: Min. 0V; Max. 0.5V
High: Min. +2.7V
z Driving Capacity:
Low: Max. +0.5V at 24mA (Sink)
High: Min. 2.4V at -3.0mA (Source)
‹
‹
Programmable Counter
z Device: 82C54-10, with a 4MHz time base
z Timer 0: DI clock source
z Timer 1: DO clock source
z Timer2: Base clock of Timer #0 and Timer #1
z Pacer Output: 0.00046Hz to 2MHz
General Specifications
z Operating Temperature: 0ºC to 60ºC
z Storage Temperature: -20ºC to 80ºC
z Humidity: 5 to 95%, non-condensing
z Connector:
PCI-7200: one 37-pin D-type and one 40-pin ribbon connector
cPCI-7200: one 100-pin SCSI-type connector
LPCI-7200S: two 68-pin SCSI-type connectors
z Dimension:
PCI-7200: Compact size, only 148mm (L) X 102mm (H)
cPCI-7200: Standard 3U CompactPCI form factor
LPCI-7200S: Low Profile PCI, 167.64mm (L) X 64.41mm (H)
z Power Consumption:
PCI-7200: +5V @ 720 mA typical
cPCI-7200: +5V @ 820 mA typical
LPCI-7200S: +5V @ 500 mA typical
z PCI signaling environment:
PCI-7200:
5V board supports a 5V PCI BUS
cPCI-7200: 3U Eurocard form factor, CompactPCI compliant
(PICMG 2.0 R2.1)
LPCI-7200S: Universal board, supports a 3.3V or 5V PCI BUS
Introduction
3
•
1.4 Software Supporting
ADLINK provides versatile software drivers and packages for users’ different
approach to building a system. We not only provide programming library for
many Windows systems, but also provide drivers for many software packages
including LabVIEW®, HP VEETM, DASYLabTM, InTouchTM, InControlTM
ISaGRAFTM, etc.
,
All software options are included in the ADLINK CD. Commercial software
drivers require licenses. Without the software license, users can still install
them and run the demo version for two hours for demonstration purpose.
Please contact an ADLINK dealer to purchase licenses.
1.4.1 Programming Library
For customers writing customized programs, we provide function libraries for
many different operating systems, including:
‹
‹
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DOS Library: Borland C/C++ and Microsoft C++ (function descriptions are
included in this user’s guide).
Windows 95 DLL: For VB, VC++, Delphi, BC5 (functions descriptions are
included in this user’s guide).
PCIS-DASK: Includes device drivers and DLLs for Windows 98,
Windows NT, and Windows 2000. The DLL is compatible across
Windows 98, Windows NT, and Windows 2000. All applications
developed with PCIS-DASK are compatible across Windows 98,
Windows NT, and Windows 2000. The developing environment can be VB,
VC++, Delphi, BC5, or any Windows programming language that allows
calls to a DLL. The PCIS-DASK user’s guide and function reference
manual are on the CD. Please refer the PDF manual files under the
\Manual_PDF\Software\PCIS-DASK
following directory:
‹
PCIS-DASK/X: Includes device drivers and a shared library for Linux.
The developing environment can be Gnu C/C++ or any programming
language that allows linking to a shared library. The PCIS-DASK/X user's
guide and function reference manual are on the CD
\Manual_PDF\Software\PCIS-DASK-X
(
).
The above software drivers are shipped with the board. Please refer to the
“Software Installation Guide” to install these drivers.
4
Introduction
•
1.4.2 PCIS-LVIEW: LabVIEW® Driver
PCIS-LVIEW contains VIs to interface with NI’s LabVIEW® software package.
PCIS-LVIEW supports Windows 95/98/NT/2000. The LabVIEW® drivers are
shipped free with the board. Users can install and use them without a license.
For detailed information about PCIS-LVIEW, please refer to the user’s guide
on the CD.
\Manual_PDF\Software\PCIS-LVIEW
(
)
1.4.3 PCIS-VEE: HP-VEE Driver
PCIS-VEE includes the user objects, which are used to interface with the HP
VEE software package. PCIS-VEE supports Windows 95/98/NT. The HP-VEE
drivers are shipped free with the board. Users can install and use them without
a license. For detailed information about PCIS-VEE, please refer to the user’s
guide on the CD.
\Manual_PDF\Software\PCIS-VEE
(
)
1.4.4 DAQBenchTM: ActiveX Controls
Customers who are familiar with ActiveX controls and VB/VC++ programming
can use the DAQBench ActiveX Control components library for developing
applications. DAQBench is designed under Windows NT/98. For more
detailed information about DAQBench, please refer to the user’s guide on the
CD.
\Manual_PDF\Software\DAQBench\DAQBench Manual.PDF
(
)
1.4.5 DASYLabTM PRO
DASYLab is an easy-to-use software package that provides easy-setup
instrument functions such as FFT analysis. Please contact ADLINK to get
DASYLab PRO, which include DASYLab and ADLINK hardware drivers.
1.4.6 PCIS-DDE: DDE Server and InTouchTM
DDE stands for Dynamic Data Exchange specifications. The PCIS-DDE
includes the PCI cards’ DDE server. The PCIS-DDE server is included on the
ADLINK CD. It requires a license. The DDE server can be used conjunction
with any DDE client under Windows NT.
Introduction
5
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1.4.7 PCIS-ISG: ISaGRAFTM driver
The ISaGRAF WorkBench is an IEC1131-3 SoftPLC control program
development environment. The PCIS-ISG includes ADLINK products’ target
drivers for ISaGRAF under the Windows NT environment. The PCIS-ISG is
included on the ADLINK CD. It requires a license.
1.4.8 PCIS-ICL: InControlTM Driver
PCIS-ICL is the InControl driver, which support the Windows NT. The
PCIS-ICL is included on the ADLINK CD. It requires a license.
1.4.9 PCIS-OPC: OPC Server
PCIS-OPC is an OPC Server that can link with OPC clients. Many software
packages on the market provide OPC clients. PCIS-OPC supports Windows
NT. It requires a license.
6
Introduction
•
2
Installation
This chapter describes how to install the PCI-7200. Package contents and
unpacking information are described. Because the PCI-7200 is a Plug and
Play device, there are no more jumper or DIP switch settings for configuration.
The interrupt number and I/O port address are assigned by the system BIOS
during system boot up.
2.1 What Included
In addition to this User's Manual, the package includes the following items:
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PCI-7200 Digital I/O & Counter Card
ACL-10437: 40-pin to 37-pin D-Sub cable
or
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cPCI-7200 Digital I/O & Counter Module for 3U CompactPCI
100-pin SCSI connector assembly
or
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LPCI-7200S Low profile Digital I/O & Counter Card
Two 68-pin SCSI connectors assembly
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ADLINK CD
Software Installation Guide
If any of these items is missing or damaged, contact the ADLINK dealer. Save
the shipping materials and carton to ship or store the product in the future.
Installation
7
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2.2 Unpacking
The PCI-7200 card contains sensitive electronic components that can be
easily damaged by static electricity.
The work area should have a grounded anti-static mat. The operator should be
wearing an anti-static wristband, grounded at the same point as the anti-static
mat.
Inspect the card module carton for obvious damage. Shipping and handling
may cause damage to the module. Be sure there is no shipping and handling
damage on the module before proceeding.
After opening the card module carton, extract the system module and place it
only on a grounded anti-static surface component side up.
Again inspect the module for damage. Press down on all the socketed IC's to
make sure that they are properly seated. Do this only with the module place on
a firm flat surface.
Note:
DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.
You are now ready to install your PCI-7200.
2.3 Device Installation for Windows Systems
Once Windows 95/98/2000 has started, the Plug and Play function of
Windows system will find the new NuDAQ/NuIPC cards. If this is the first time
to installing NuDAQ/NuIPC cards in this system, Windows will require device
information source. Please refer to the “Software Installation Guide” for the
steps of installing the device.
8
Installation
•
2.4 PCI-7200/cPCI-7200/LPCI-7200S’s Layout
Figure 2.1(a) PCI-7200 Layout Diagram
Installation
9
•
Figure 2.1(b) cPCI-7200 Layout Diagram
10 Installation
•
CN1A
CN1B
Figure 2.1(c) LPCI-7200S Layout Diagram
Installation 11
•
Figure 2.1(d) LPCI-7200S with standard PCI bracket Layout Diagram
12 Installation
•
2.5 Hardware Installation Outline
Hardware configuration
These PCI cards (or CompactPCI, Low Profile PCI cards) are equipped with a
Plug and Play PCI controller that requests base addresses and interrupts
according to PCI standard. The system BIOS will install the system resource
based on the PCI cards’ configuration registers and system parameters (which
are set by system BIOS). Interrupt assignment and memory usage (I/O port
locations) of the PCI cards can be assigned by system BIOS only. These
system resource assignments are done on a board-by-board basis. It is not
suggested to assign the system resource by any other methods.
PCI slot selection
The PCI and Low-Profile PCI cards can be inserted to any PCI slot without any
configuration for system resource. CompactPCI peripheral slots are marked
with a circle on the backplane. Please note that the PCI, CompactPCI, and
Low-Profile PCI system board must provide bus-mastering capability to
operate this board well.
Installation Procedures
1. Turn off the computer
2. Turn off all accessories (printer, modem, monitor, etc.) connected to the
computer
3. Remove the cover from your computer
4. Select a 32-bit PCI slot. PCI slot are short than ISA or EISA slots, and are
usually white or ivory
5. Before handling the PCI cards, discharge any static buildup on your body by
touching the metal case of the computer. Hold the edge of the card and do
not touch the components
6. Position the board into the PCI selected slot.
7. Secure the card in place at the rear panel of the system
Running 7200UTIL.EXE
The IRQ number and I/O port address can be configured by the system. Use
7200UTIL.EXE
the
utility to displayed the above values. A testing program is
included in this utility to check if the PCI-7200 can work properly. Refer to
Section 5.2 for further information.
Installation 13
•
2.6 Connector Pin Assignments
2.6.1 PCI-7200 Pin Assignments
The PCI-7200 comes equipped with one 37-pin D-Sub connector (CN2)
located on the rear mounting plate and one 40-pin female flat cable header
connector (CN1). The CN2 is located on the rear mounting plate; the CN1 is on
front of the board. Refer section 2.4 PCI-7200‘s layout.
CN2 is used for digital inputs (DI 0 to DI 15) and digital outputs (DO 0 to DO 15)
The reminding digital I/O channels DI 16 to DI 31 and DO 16 to DO 31 are on
CN1. The pin assignment of CN1 and CN2 is illustrated in the Figures 2.2 and
2.3.
Legend:
DO n : Digital Output CH n
DI n : Digital Input CH n
GND : Ground
ACK : ACK handshaking signal
REQ : REQ handshaking signal
I_TRG: Input signal to start DI data sampling
O_TRG: Output signal can be controlled by software
1
2
DI16
DI17
DI18
DI19
DI20
DI21
DI22
DI23
DI24
DI25
DI26
DI27
DI28
DI29
DI30
DI31
+5V
DO16
DO17
DO18
DO19
DO20
DO21
DO22
DO23
DO24
DO25
DO26
DO27
DO28
DO29
DO30
DO31
GND
3
4
5
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
O_ACK
O_REQ
N/C
O_TR1
N/C
N/C
Figure 2.2 CN1 Pin Assignments
14 Installation
•
1
2
3
DI 0
DI 1
DI 2
DI 3
20
21
DO0
DO1
DO2
DO3
DO4
DO5
22
23
24
25
4
5
DI 4
DI 5
DI 6
6
7
26
27
8
DO6
DO7
DO8
DO9
DO10
DI 7
DI 8
DI 9
DI10
DI11
9
28
29
10
11
12
13
30
31
32
DO11
DO12
DO13
DO14
DO15
GND
DI12
DI13
DI14
DI15
+5V
14
15
16
17
33
34
35
36
37
18
19
I_ACK
I_REQ
I_TRG
Figure 2.3 CN2 Pin Assignments
Installation 15
•
2.6.2 cPCI-7200 Pin Assignments
(1)
(2)
(3)
(51
(52
(53
(1) DO0
(26) O_TRG (51) DO1
(27) O_REQ (52) DO3
(28) O_ACK (53) DO5
(29) AUXIN2 (54) DO7
(30) AUXIN3 (55) DO9
(76) GND
(77) GND
(78) GND
(79) AuxOut2
(80) AuxOut3
(81) GND
(82) GND
(83) GND
(84) DIN1
(85) DIN3
(86) DIN5
(87) DIN7
(88) DIN9
(89) DIN11
(90) DIN13
(91) DIN15
(92) GND
(93) DIN17
(94) DIN19
(95) DIN21
(2) DO2
(3) DO4
(4) DO6
(5) DO8
(6) DO10
(7) DO12
(8) DO14
(9) GND
(31) +5Vout
(32) +5Vout
(33) GND
(34) DIN0
(35) DIN2
(36) DIN4
(37) DIN6
(38) DIN8
(39) DIN10
(40) DIN12
(41) DIN14
(42) GND
(43) DIN16
(44) DIN18
(45) DIN20
(56) DO11
(57) DO13
(58) DO15
(59) GND
(60) DO17
(61) DO19
(62) DO21
(63) DO23
(64) DO25
(65) DO27
(66) DO29
(67) DO31
(68) GND
(69) GND
(70) GND
(10) DO16
(11) DO18
(12) DO20
(13) DO22
(14) DO24
(15) DO26
(16) DO28
(17) DO30
(18) GND
(19) +5Vout
(20) +5Vout
(48)
(49)
(50)
(9
(21) AUXIN0 (46) DIN22
(71) AuxOut0 (96) DIN23
(72) AuxOut1 (97) DIN25
(9
(1
(22) AUXIN1 (47) DIN24
(23) I_TRG
(48) DIN26
(49) DIN28
(50) DIN30
(73) GND
(74) GND
(75) GND
(98) DIN27
(99) DIN29
(100) DIN31
(24) I_REQ
(25) I ACK
Figure 2.4 CN Pin Assignments
16 Installation
•
2.6.3 LPCI-7200S Pin Assignments
DIN0 A1 A35 GND
DIN1 A2 A36 GND
DIN2 A3 A37 GND
DIN3 A4 A38 GND
DIN4 A5 A39 GND
DIN5 A6 A40 GND
DIN6 A7 A41 GND
DIN7 A8 A42 GND
DIN8 A9 A43 GND
DIN9 A10 A44 GND
DIN10 A11 A45 GND
DIN11 A12 A46 GND
DIN12 A13 A47 GND
DIN13 A14 A48 GND
DIN14 A15 A49 GND
DIN15 A16 A50 GND
DIN16 A17 A51 GND
DIN17 A18 A52 GND
DIN18 A19 A53 GND
DIN19 A20 A54 GND
DIN20 A21 A55 GND
DIN21 A22 A56 GND
DIN22 A23 A57 GND
DIN23 A24 A58 GND
DIN24 A25 A59 GND
DIN25 A26 A60 GND
DIN26 A27 A61 GND
DIN27 A28 A62 GND
DIN28 A29 A63 GND
DIN29 A30 A64 GND
DIN30 A31 A65 GND
DIN31 A32 A66 GND
I_REQ A33 A67 I_ACK
I_TRG A34 A68 5Vout
Figure 2.5 CN1A Pin Assignments
Installation 17
•
DOUT0 B1 B35 GND
DOUT1 B2 B36 GND
DOUT2 B3 B37 GND
DOUT3 B4 B38 GND
DOUT4 B5 B39 GND
DOUT5 B6 B40 GND
DOUT6 B7 B41 GND
DOUT7 B8 B42 GND
DOUT8 B9 B43 GND
DOUT9 B10 B44 GND
DOUT10 B11 B45 GND
DOUT11 B12 B46 GND
DOUT12 B13 B47 GND
DOUT13 B14 B48 GND
DOUT14 B15 B49 GND
DOUT15 B16 B50 GND
DOUT16 B17 B51 GND
DOUT17 B18 B52 GND
DOUT18 B19 B53 GND
DOUT19 B20 B54 GND
DOUT20 B21 B55 GND
DOUT21 B22 B56 GND
DOUT22 B23 B57 GND
DOUT23 B24 B58 GND
DOUT24 B25 B59 GND
DOUT25 B26 B60 GND
DOUT26 B27 B61 GND
DOUT27 B28 B62 GND
DOUT28 B29 B63 GND
DOUT29 B30 B64 GND
DOUT30 B31 B65 GND
DOUT31 B32 B66 GND
O_REQ B33 B67 O_ACK
O_TRG B34 B68 5Vout
Figure 2.6 CN1B Pin Assignments
18 Installation
•
2.7 8254 for Timer Pacer Generation
8254 Timer/Counter
Timer 0
CLK0
GATE0
Digital Input Timer Pacer
OUT0
“H”
Timer 1
Timer 2
CLK1
Digital Output Timer Pacer
GATE1
OUT1
OUT2
“H”
4MHz Clock
CLK2
GATE2
“H”
Figure 2.7 8254 configuration
The internal timer/counter 8254 on the PCI-7200 is configured as the above
diagram (Figure 2.7). Users can use it to generate the timer pacer for both
digital input and digital output triggers.
The digital input timer pacer is from OUT0 (Timer 0), and the digital output
timer pacer is from OUT1 (Timer 1). Besides, Timer 0 and Timer 2 can be
cascaded together to generate more timer pacer frequencies for digital input.
Also, Timer 2 can be cascaded with Timer 1 for digital output.
pacer rate = 4MHz / ( C0 * C2)
if Timer 0 & Timer 2 are cascaded
pacer rate = 4MHz / C0
if timer 0 & Timer 2 are not cascaded
The maximum pacer signal rate of input and output are 4MHz/2 = 2Mhz. The
minimum signal rate is 4MHz/65535/65535.
For example, to get a pacer rate of 2.5kHz, set C0 = 40 and C2 = 40. That is
2.5KHz = 4Mhz / (40 x 40)
Installation 19
•
2.8 LPCI-7200S PCI Bus Signaling
Low-Profile PCI is a new PCI card standard for space-constrained system
designs. The new form factor maintain the same electrical protocols, PCI signals,
and software drivers as standard PCI v2.2 expansion cards. However,
Low-Profile PCI bus interface only supports 3.3V signaling. To support both 5V
and 3.3V signaling, LPCI-7200S implements 5V I/O tolerant bus switches to
achieve the I/O voltage transition. This allows LPCI-7200S to be used in both 5V
and 3.3V systems.
2.9 Onboard Pull-ups and Terminations in digital input
The PCI-7200, cPCI-7200 and LPCI-7200S have 32 digital input channels.
On-board pull-ups and terminations for digital input circuits may be needed for
some applications. The pull-ups guarantee a fixed input state when
external connections are floating. Schottky terminations can minimize
undershoot/overshoot disturbances caused by reflection noise on high-speed
bus lines. Table 2.1 lists the pull-ups and termination status of PCI-7200,
cPCI-7200 and LPCI-7200S. Figure 2.8 is the illustration of the pull-up resistor
and terminations on-board.
Pull-up resistor
None
Terminations
None
PCI-7200
Schottky diode clamped
to ground & power
Schottky diode clamped
to ground & power
cPCI-7200
None
LPCI-7200S
10kΩ
Table 2.1 pull-ups and termination of PCI/cPCI-7200 and LPCI-7200S.
VCC
D-type
Flip-Flop
D
Q
Digital input
GND
Figure 2.8 Digital input pull-up resistor and termination circuit diagram.
20 Installation
•
3
Register Format
3.1 I/O Registers Format
The PCI-7200 occupies 8 consecutive 32-bit I/O addresses in the PC I/O
address space. The cPCI-7200 occupies 9 consecutive 32-bit I/O addresses.
Table 4.1 shows the I/O Map
Address
Read
Write
Base + 0
Base + 4
Base + 8
Base + C
Base + 10
Counter 0
Counter 1
Counter 2
Counter 0
Counter 1
Counter 2
CLK Control CW0
---
---
Digital Input Reg.
Digital Output
(Read-back)
DIO Status & Control
INT Status & Control
Base + 14
Digital Output Reg.
Base + 18
Base + 1C
Base + 20
(cPCI-7200
only)
DIO Status &Control
INT Status & Control
AUXDIO Reg.
AUXDO Reg.
Note:
(1) I/O port is 32-bits wide
(2) 8-bit or 16-bit I/O access is not allowed
Register Format 21
•
3.2 Digital Input Register (BASE + 10)
32 digital input channels can be read from this register
Address: BASE + 10
Attribute: READ Only
Data Format:
Byte
7
6
5
4
3
2
1
0
Base +10
Base +11
Base +12
Base +13
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI9
DI17
DI25
DI0
DI8
DI16
DI24
DI15
DI23
DI31
DI14
DI22
DI30
DI13
DI21
DI29
DI12
DI20
DI28
DI11
DI19
DI27
DI10
DI18
DI26
3.3 Digital Output Register (BASE + 14)
32 digital output channels can be written and read to/from this register
Address: BASE + 14
Attribute: READ/WRITE
Data Format:
Byte
7
6
5
4
3
2
1
0
Base +14
Base +15
Base +16
Base +17
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
DO8
DO15 DO14 DO13 DO12 DO11 DO10 DO9
DO23 DO22 DO21 DO20 DO19 DO18 DO17 DO16
DO31 DO30 DO29 DO28 DO27 DO26 DO25 DO24
The digital output status can be read back through the same location (BASE +
14)
3.4 DIO Status & Control Register (BASE + 18)
The data transfer mode of digital input is controlled and status is checked
through this register.
Address: BASE + 18
Attribute: READ/WRITE
Data Format:
Byte
7
6
5
4
3
2
1
0
Base +18 O_ACK DIN_EN I_TRG TRGPL I_FIFO
I_TIME0 I_REQ
I_ACK
Base +19 ----
Base +20 ----
Base +21 ----
I_OVER ----
----
----
----
O_TRG O_FIFO O_TIME1 O_REQ
----
----
----
----
----
----
----
----
----
----
O_UND
----
22 Register Format
•
‹
Digital Input Mode Setting:
I_ACK: Input ACK Enable
1: Input ACK is enabled (input ACK will be asserted after input data is
read by CPU or written to input FIFO)
0: Input ACK is disabled
I_REQ: Input REQ Strobe Enabled
1: Use I_REQ edge to latch input data
0: I_REQ is disabled
I_TIME0: Input Timer 0 Enable
1: Input is sampled by falling edge of Counter 0 output (COUT0)
0: Input Timer 0 is disabled
I_FIFO: Input FIFO Enable Mode
1: Input FIFO is enabled (input data is saved to input FIFO)
0: Input FIFO is disabled
TRGPOL: Input Trigger Polarity
1: I_TRG is Rising Edge Active
0: I_TRG is Falling Edge Active
I_TRG: External Trigger Enable
1: Wait until I_TRG signal is active, digital input sampling will begin
after a rising or falling edge of I_TRG
0: Start input sampling immediately (if input control register is set)
DIN_EN: Digital Input Enable
1: Digital Input Enable
0: Digital Input Disabled, when this bit is set as 0, all digital input
operation will be stopped
‹
Digital Output Mode Setting:
O_ACK: Output ACK Enable
1: Output ACK is enabled; the output circuit will wait for O_ACK after
O_REQ strobe is asserted
0: Output ACK is disabled
O_REQ: Output REQ Enable
1: Output REQ is enabled; an O_REQ strobe will be generated after
output data is ready
0: Output REQ is disabled
O_TIME1: Output Timer 1 Enable
1: Output Timer 1 is enabled; output data is moved from output FIFO
to DO registers when output of Counter1 goes low
0: Output Counter 1 is disabled
O_FIFO: Output FIFO Enable
1: Output FIFO is enabled (output data is moved from output FIFO)
0: Output FIFO is disabled
Register Format 23
•
O_TRG: Digital Output Trigger Signal
This bit is used to control the O_TRG output of PCI-7200; the signal is
on CN1 pin 36 of PCI-7200, CN1 pin 26 of cPCI-7200, CN2 pin 34 of
LPCI 7200S when
1: O_TRG 1 goes High (1)
0: O_TRG 1 goes Low (0)
‹
Digital I/O FIFO Status:
I_OVR: Input data overrun
1: Digital Input FIFO is full (overrun) during input data transfer
0: No input data overrun occurred
Input data overrun occurred, the I_OVR bit is set when input FIFO is
full and there is new input data coming in. This bit can be cleared by
writing “1” to it.
O_UND: Output data FIFO is underrun
1: Output FIFO is empty during output data transfer
0: No output data underrun occurred
Output data underrun, the O_UND bit is set when output FIFO is
empty and the output request for new data, this bit can be cleared by
writing “1” to it.
3.5 Interrupt Status & Control Register (BASE + 1C)
The interrupt mode/status is set/checked through this register.
Address: BASE + 1C
Attribute: READ/WRITE
Data Format:
Byte
Base +1C SI_TO
Base +1D FIFOFF FIFOEF FIFORST REQ_NEG T1_T2 T0_T2 SI_T2
7
6
5
4
3
2
1
0
SI_REQ SO_ACK T2_EN
T1_EN T0_EN II_REQ IO_ACK
SI_T1
----
----
Base +1E ----
Base +1F ----
----
----
----
----
----
----
----
----
----
----
----
----
‹
Interrupt Control:
With the PCI-7200, interrupts can be triggered by many signal sources such as
O_ACK, I_REQ, timer 0, timer 1, and timer 2. The following bits control the
interrupt source:
IO_ACK: Interrupt is triggered by O_ACK signal.
1: O_ACK interrupt is enabled
0: O_ACK interrupt is disabled
II_REQ: Interrupt is triggered by I_REQ signal.
1: I_REQ interrupt is enabled
0: I_REQ interrupt is disabled
24 Register Format
•
T0_EN: Interrupt is triggered by timer 0 output.
1: Timer 0 interrupt is enabled
0: Timer 0 interrupt is disabled
T1_EN: Interrupt is triggered by timer 1 output.
1: Timer 1 interrupt is enabled
0: Timer 1 interrupt is disabled
T2_EN: Interrupt is triggered by timer 2 output.
1: Timer 2 interrupt is enabled
0: Timer 2 interrupt is disabled
‹
Interrupt Status:
The following bits are used to check interrupt status:
SO_ACK: Status of O_ACK interrupt
1: O_ACK Interrupt occurred
0: No O_ACK interrupt
SI_REQ: Status of I_REQ interrupt
1: I_REQ Interrupt occurred
0: No I_REQ Interrupt
SI_T0: Status of timer 0 interrupt
1: OUT0 (output of timer 0) Interrupt occurred
0: No timer 0 Interrupt
SI_T1: Status of timer 1 interrupt
1: OUT1 (output of timer 1) Interrupt occurred
0: No timer 1 Interrupt
SI_T2: Status of timer 2 interrupt
1: OUT2 (output of timer 2) interrupt occurred
0: No timer 2 Interrupt
Note: Writing “1” to the corresponding bit of the register can clear all
interrupt statuses. In order to make the interrupt work properly, the
interrupt service routine has to clear all the interrupt status before end
of the ISR.
‹
Timer Configuration Control:
The 8254 timer on the PCI-7200 can be configured as either timer 0 cascaded
with timer 2 or timer 1 cascaded with timer 2. These configurations are
controlled by the following bits:
T0_T2: Timer 0 is cascaded with timer 2
1: Timer 0 and timer 2 are cascaded together; output of timer 2
connects to the clock input of timer 0.
0: Not cascaded, the 4MHz clock is connected to the timer 0 clock
input.
Register Format 25
•
T1_T2: Timer 1 is cascaded with timer 2
1: Timer 1 and timer 2 are cascaded together; output of timer 2
connects to the clock input of timer 1.
0: Not cascaded, the 4MHz clock is connected to the timer 1 clock
input.
‹
I_REQ Polarity Selection:
When the input sampling is controlled by the I_REQ signal only, the I_REQ
can be programmed to be rising edge active or falling edge active.
REQ_NEG: I_REQ trigger polarity
1: latch input data on falling edge of I_REQ
0: latch input data on rising edge of I_REQ
‹
FIFO Control and Status (cPCI-7200 only):
The cPCI-7200 has an extra 2k samples digital input FIFO. The FIFO can be
cleared and monitored by the following bits:
FIFORST (Write only): Clear the on-board DI FIFO
1: Write 1 to clear the data of the FIFO.
0: No operation.
FIFOEF (Read only): Empty flag of the DI FIFO
1: DI FIFO is empty.
0: DI FIFO is not empty.
FIFOFF (Read only): Full flag of the DI FIFO
1: DI FIFO is full.
0: DI FIFO is not full.
Note: The cPCI-7200 has 2 cascaded DI FIFOs. One is located in the PCI
controller chip, the other one is on the PCI-7200 board. The above
bits only control the on-board FIFO. In order to control the on-chip
FIFO, please refer to the AMCC-5933 data book.
26 Register Format
•
3.6 8254 Timer Registers (BASE + 0)
The 8254 timer/counter IC occupies 4 I/O address. Users can refer to Tundra's
or Intel's data sheet for a full description of the 8254 features. Download the
8254 data sheet from the following web site:
Address
Read
Write
Base + 0
Base + 4
Base + 8
Base + C
Counter 0
Counter 1
Counter 2
---
Counter 0
Counter 1
Counter 2
CLK Control CW0
Register Format 27
•
4
Operation Theory
In PCI-7200, there are four data transfer modes can be used for digital I/O
access and control, these modes are:
1. Direct Program Control: the digital inputs and outputs can be read/written
and controlled by its corresponding I/O port address directly.
2. Internal Timer Pacer Mode: the digital input and output operations are
paced by an internal timer pacer and are transferred by bus mastering DMA.
3. External Clock Mode: the digital input operation is clocked by external
I_REQ strobe and transferred by bus mastering DMA.
4. Handshaking: through REQ and ACK signals, the digital I/O can have
simple handshaking data transfers.
4.1 Direct Program Control
Digital I/O operations can be controlled by I/O port BASE+10 for digital input
and BASE+14 for digital output.
The I/O port address BASE is assigned by system BIOS, please refer to
Section 5 for a more detailed description.
The digital OUT operation is:
outport (BASE+14, 0xAAAAAAAA) // (A : 0 to F)
The digital IN operation is:
value = inport (BASE+10)
// The input status is save in the
// value variable
Operation Theory 29
•
4.2 Timer Pacer Mode
The digital I/O access control is clocked by timer pacer, which is generated by
an interval programming timer/counter chip (8254). There are three timers on
the 8254. Timer 0 is used to generate timer pacer for digital input and timer 1 is
used for digital output. The configuration is illustrated as below.
8254 Timer/Counter
Timer 0
CLK0
Digital Input Timer Pacer
Digital Output Timer Pacer
GATE0
OUT0
“H”
Timer 1
Timer 2
CLK1
GATE1
OUT1
OUT2
“H”
4MHz Clock
CLK2
GATE2
“H”
The operation sequences are:
1. Define the frequency (timer pacer rate)
2. The digital input data are saved in FIFO after a timer pacer pulse is
generated. The sampling is controlled by timer pacer.
3. The data saved in FIFO will be transferred to main memory of the computer
system directly and automatically. This is controlled by bus mastering DMA
control, this function is supported by PCI controller chip.
The operation flow is show as following:
8254 Timer/Counter
1
Timer 0
To Digital Input Trigger
CLK0
GATE0
OUT0
Latch Digital Input
2
3
PC's Main Memory
Bus mastering
DMA data Transfer
Digital Input FIFO
30 Operation Theory
•
4.3 External Clock Mode
The digital input is clocked by external strobe, which is from Pin 19 (I_REQ) of
CN2 (PCI-7200), Pin 24 of CN1 (cPCI-7200), or PIN 33 of CN1A (LPCI-7200S).
The operation sequence is very similar to the Timer Pacer Trigger. The only
difference is the clock source.
1. The external input strobe is generated from outside device, and goes
through the Pin 19 (I_REQ) of CN2 to latch the digital input.
2. The digital input data is saved in FIFO after an I/O strobe signal is coming in.
3. The data saved in input FIFO will be transferred to main memory on your
computer system directly. This is controlled by bus mastering DMA control,
this function is supported by PCI.
1
To Digital Input Trigger
Latch Digital
Input Data
Pin 19 of CN2
2
3
PC's Main Memory
Bus mastering
DMA data Transfer
Digital Input FIFO
4.4 Handshaking
The PCI-7200 also supports a handshaking digital I/O transfer mode. That is,
after input data is ready, an I_REQ is sent from an external device, and I_ACK
will go high to acknowledge the data already accessed.
I_REQ & I_ACK for Digital Input
1. Digital Input Data is ready.
2. An I_REQ signal is generated for digital input operation.
3. Digital input data is saved to FIFO.
4. An I_ACK signal is generated and sent to an outside device.
5. If the FIFO is not empty and PCI bus is not occupied, the data will be
transferred to main memory.
Operation Theory 31
•
Digital Input DATA
1
2
IN_REQ
IN_ACK
Latch Digital Input
or Digital Output
3
4
PC's Main Memory
Bus mastering
DMA data Transfer
Digital Input FIFO
5
O_REQ & O_ACK for Digital Output
1. Digital Output Data is moved from PC memory to FIFO of PCI-7200 by using
DMA data mastering data transfer.
2. Move output data from FIFO to digital output circuit.
3. Output data is ready.
4. An O_REQ signal is generated and sent to outside device.
5. After an O_ACK is captured, steps 2-5 will be repeated.
** If the FIFO is not full, the output data is moved form PC‘s main memory to
FIFO automatically.
Digital Output DATA
4
3
O_REQ
Move Data to
Digital Output
O_ACK
5
2
PC's Main
Memory
Bus mastering
Digital Output FIFO
DMA data Transfer
1
32 Operation Theory
•
4.5 Timing Characteristic
1. I_REQ as input data strobe (Rising Edge Active)
t
h
l
t
IN_ I_REQ
cyc
t
valid data
D10~DI31
valid data
s
t tn
th ≥ 60ns
ts ≥ 2ns
tI ≥ 60ns
tn ≥ 30ns
tCYC ≥ 5 PCI CLK Cycle
2. I_REQ as input data strobe (Falling Edge Active)
t
h
l
t
IN_R I_REQ
D10~DI31
cyc
t
valid data
valid data
s
t tn
th ≥ 60ns
ts ≥ 2ns
tI ≥ 60ns
tCYC ≥ 5 PCI CLK Cycle
tn ≥ 30ns
Operation Theory 33
•
3. I_REQ & I_ACK Handshaking
t5
IN I_REQ
IN I_ACK
t3
t4
valid data
D10~DI31
valid data
t1
t2
t1 ≥ 0ns
t2 ≥ 0ns
t5 ≥ 60ns
t4 ≥ 1 PCI CLK Cycle
t3 ≥ 2 PCI CLK Cycle
Note: I_REQ must be asserted until I_ACK asserts, I_ACK will be asserted
until I_REQ de-asserts.
4. O_REQ as output data strobe
t
h
Out O_REQ
cyc
t
valid data
D00~D031
valid data
s
t
ts ≥ 19ns
th ≥ 2 PCI CLK Cycles Tcyc ≥ 500ns
34 Operation Theory
•
5. O_REQ & O_ACK Handshaking
t3
OUT
O_REQ
2
t
OUT_
O_ACK
valid data
valid data
DO0~Do31
1
t
5 PCI CLK Cycle
1 PCI CLK Cycle
t3
1
19ns
t
t2
Note: O_ACK must be de-asserted before O_REQ asserts, O_ACK can be
asserted any time after O_REQ asserts, O_REQ will be reasserted
after O_ACK is asserted.
Operation Theory 35
•
5
C/C++ Libraries
This chapter describes the software library for operating the card. Only
functions in DOS library and Windows 95 DLL are described. Please refer to
the PCIS-DASK function reference manual, which included on the ADLINK CD,
for the descriptions of the Windows 98/NT/2000 DLL functions.
The function prototypes and some useful constants are defined in the header
LIB
INCLUDE
directory (Windows 95). For the
files
directory (DOS) and
Windows 95 DLL, the developing environment can be Visual Basic 4.0 or
above, Visual C/C++ 4.0 or above, Borland C++ 5.0 or above, Borland Delphi
2.x (32-bit) or above, or any Windows programming language that allows calls
to a DLL. C/C++, VB, and Delphi files are included.
5.1 Libraries Installation
Please refer to the “Software Installation Guide” for the detailed information
about how to install the software libraries for DOS, or Windows 95 DLL, or
PCIS-DASK for Windows 98/NT/2000.
Device drivers and DLL functions of Windows 98/NT/2000 are included in the
PCIS-DASK. Please refer to the PCIS-DASK user’s guide and function
reference, which included on the ADLINK CD, for detailed programming
information.
C/C++ Libraries 37
•
5.2 Programming Guide
5.2.1 Naming Convention
The functions of the NuDAQ PCI cards or NuIPC CompactPCI cards’ software
drivers use full-names to represent the functions' real meaning. The naming
convention rules are:
In DOS:
_7200_Initial()
_{hardware_model}_{action_name}. e.g.
.
All functions in the PCI-7200 driver are named with 7200 as {hardware_model}.
But they can be used by PCI-7200, cPCI-7200 and LPCI-7200S.
In order to recognize the difference between DOS library and Windows 95
W
library, a capital " " is put on the head of each function name of the Windows
W_7200_Initial()
95 DLL driver (e.g.
).
5.2.2 Data Types
Some data types are definded in Pci_7200.h (DOS) and Acl_pci.h (Windows
95). These data types are used by NuDAQ Cards’ library. We suggest using
these data types. The following table shows the data type names and their
range.
Type Name
U8
I16
U16
I32
U32
Description
8-bit ASCII character
16-bit signed integer
16-bit unsigned integer
32-bit signed integer
32-bit single-precision
floating point
Range
0 to 255
-32768 to 32767
0 to 65535
-2147483648 to 2147483647
0 to 4294967295
F32
32-bit single-precision
floating point
-3.402823E38 to 3.402823E38
F64
64-bit double-precision
floating point
Boolean logic value
-1.797683134862315E308 to
1.797683134862315E309
TRUE, FALSE
Boolean
38 C/C++ Libraries
•
5.3 _7200_Initial
@ Description
A PCI-7200 card is initialized according to the card number.
Because the PCI-7200 is PCI bus architecture and meets the Plug and Play
design, the IRQ and base_address (pass-through address) are assigned
by system BIOS directly. Every PCI-7200 card has to be initialized by this
function before calling other functions.
Note: Because the configuration of PCI-7200 is handled by the system, there
are no jumpers or DMA selection on the PCI boards that need to be set
up by the users.
@ Syntax
Visual C++ (Windows 95)
int W_7200_Initial (U8 card_number, U16 *base_addresss, U8
*irq_no)
Visual Basic (Windows 95)
W_7200_Initial (ByVal card_number As Byte,
base_addresss As Integer, irq_no As Byte) As Long
C/C++ (DOS)
int _7200_Initial (U8 card_number, U16 *base_addresss,
U8 *irq_no)
@ Argument
card_number: the card number to be initialized, only four cards can be
initialized, the card number must be CARD_1, CARD_2, CARD_3 or
CARD_4.
base_address: the I/O port base address of the card, it is assigned by the
system BIOS.
irq_no: the system will give an available interrupt number to this card
automatically.
@ Return Code
ERR_NoError
ERR_InvalidBoardNumber
ERR_PCIBiosNotExist
ERR_PCICardNotExist
ERR_PCIIrqNotExist
ERR_BaseAddressError
C/C++ Libraries 39
•
5.4 _7200_Switch_Card_No
@ Description
After initializing more than one PCI-7200 card, this function is used to select
which card is currently used.
@ Syntax
Visual C++ (Windows 95)
int W_7200_Switch_Card_No (U8 card_number)
Visual Basic (Windows 95)
W_7200_Switch_Card_No (ByVal card_number As Byte) As
Long
C/C++ (DOS)
int _7200_Switch_Card_No (U8 card_number)
@ Argument
card_number: The card number to be initialized, four cards can be
initialized, the card number must be CARD_1, CARD_2, CARD_3, or
CARD_4, but only one card is active.
@ Return Code
ERR_NoError
ERR_InvalidBoardNoInit
5.5 _7200_AUX_DI
@ Description
Read data from auxiliary digital input port of cPCI-7200 card. You can get all
4 bits input data by using this function.
@ Syntax
Visual C++ (Windows 95)
int W_7200_AUX_DI (U32 *aux_di)
Visual Basic (Windows 95)
W_7200_DI (aux_di As Long) As Long
C/C++ (DOS)
int _7200_DI (U32 *aux_di)
@ Argument
aux_di: returns 4-bit value from auxiliary digital input port.
@ Return Code
ERR_NoError
ERR_FunctionNotAvailable
40 C/C++ Libraries
•
5.6 _7200_AUX_DI_Channel
@ Description
Read data from the auxiliary digital input channel of cPCI-7200 card. There
are 4 digital input channels on the cPCI-7200 auxiliary digital input port.
When performing this function, the auxiliary digital input port is read and the
value of the corresponding channel is returned.
* channel means each bit of digital input port.
@ Syntax
Visual C++( Windows 95)
int W_7200_AUX_DI_Channel (U8 di_ch_no, Boolean
*aux_data)
Visual Basic (Windows 95)
W_7200_AUX_DI_Channel (ByVal di_ch_no As Byte,
aux_data As Byte) As Long
C/C++ ( DOS)
int _7200_AUX_DI_Channel (U8 di_ch_no, Boolean
*aux_data)
@ Argument
di_ch_no: the DI channel number, the value is between 0 and 3.
aux_data: return value, either 0 or 1.
@ Return Code
ERR_NoError, ERR_InvalidDIChannel,ERR_FunctionNotAvailable
5.7 _7200_AUX_DO
@ Description
Write data to auxiliary digital output port. There are 4 auxiliary digital outputs
on the cPCI-7200.
@ Syntax
Visual C++ (Windows 95)
int W_7200_AUX_DO (U32 aux_do)
Visual Basic (Windows 95)
W_7200_AUX_DO (ByVal aux_do As Long) As Long
C/C++ (DOS)
int _7200_AUX_DO (U32 aux_do)
@ Argument
aux_do: value will be written to auxiliary digital output port.
@ Return Code
ERR_NoError
ERR_FunctionNotAvailable
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5.8 _7200_AUX_DO_Channel
@ Description
Write data to auxiliary digital output channel (bit). There are 4 auxiliary digital
output channels on the cPCI-7200. When performing this function, the
digital output data is written to the corresponding channel.
* channel means each bit of digital input port
@ Syntax
Visual C++ (Windows 95)
int W_7200_AUX_DO_Channel (U8 do_ch_no, Boolean aux_data)
Visual Basic (Windows 95)
W_7200_AUX_DO_Channel (ByVal do_ch_no As Byte, ByVal
aux_data As Byte) As Long
C/C++ (DOS)
int _7200_AUX_DO_Channel (U8 do_ch_no, Boolean aux_data)
@ Argument
do_ch_no: the auxiliary DO channel number, the value is between 0 and 3.
aux_data: either 0 (OFF) or 1 (ON).
@ Return Code
ERR_NoError
ERR_InvalidDOChannel
ERR_FunctionNotAvailable
5.9 _7200_DI
@ Description
This function is used to read data from digital input port. There are 32-bit
digital inputs on the PCI-7200. Use this function to get all 32 inputs data from
_7200_DI.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DI (U32 *di_data)
Visual Basic (Windows 95)
W_7200_DI (di_data As Long) As Long
C/C++ (DOS)
int _7200_DI (U32 *di_data)
@ Argument
di_data: returns all 32-bit value from digital port.
@ Return Code
ERR_NoError
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5.10 _7200_DI_Channel
@ Description
This function is used to read data from digital input channels (bit). There are
32 digital input channels on the PCI-7200. When performs this function, the
digital input port is read and the value of the corresponding channel is
returned.
* channel means each bit of digital input port.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DI_Channel (U8 di_ch_no, Boolean *di_data)
Visual Basic (Windows 95)
W_7200_DI_Channel (ByVal di_ch_no As Byte, di_data As Byte)
As Long
C/C++ (DOS)
int _7200_DI_Channel (U8 di_ch_no, Boolean *di_data)
@ Argument
di_ch_no: the DI channel number, the value has to be set within 0 and 31.
di_data: return value, either 0 or 1.
@ Return Code
ERR_NoError
ERR_InvalidDIChannel
5.11 _7200_DO
@ Description
This function is used to write data to the digital output port. There are 32
digital outputs on the PCI-7200.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DO (U32 do_data)
Visual Basic (Windows 95)
W_7200_DO (ByVal do_data As Long) As Long
C/C++ (DOS)
int _7200_DO (U32 do_data)
@ Argument
do_data: value will be written to digital output port
@ Return Code
ERR_NoError
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5.12 _7200_DO_Channel
@ Description
This function is used to write data to digital output channels (bit). There are
32 digital output channels on the PCI-7200. When performing this function,
the digital output data is written to the corresponding channel.
* channel means each bit of digital input port
@ Syntax
Visual C++ (Windows 95)
int W_7200_DO_Channel (U8 do_ch_no, Boolean do_data)
Visual Basic (Windows 95)
W_7200_DO_Channel (ByVal do_ch_no As Byte, ByVal do_data As
Byte) As Long
C/C++ (DOS)
int _7200_DO_Channel (U8 do_ch_no, Boolean do_data)
@ Argument
do_ch_no: the DO channel number, the value has to be set within 0 and 31.
do_data: either 0 (OFF) or 1 (ON).
@ Return Code
ERR_NoError
ERR_InvalidDOChannel
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5.13 _7200_Alloc_DMA_Mem
@ Description
Contact Windows 95/98 system to allocate a block of contiguous memory
for single-buffered DMA transfer. This function is only available in Windows
95/98.
@ Syntax
Visual C++ (Windows 95)
int W_7200_Alloc_DMA_Mem (U32 *buff, U32 *handle, U32
buf_size, U32 *actual_size)
Visual Basic (Windows 95)
W_7200_Alloc_DMA_Mem (buff As Long, handle As Long, ByVal
buf_size As Long, actual_size As Long ) As Long
@ Argument
buff: The start address of the user buffer for DMA data transfer. This buffer
will be attached to the DMA memory allocated by this function. When using
this DMA memory handle as an argument of the W_7200_DI_DMA_Start
function, DI data will be copied to this buffer. When using this DMA memory
handle as an argument of the W_7200_DO_DMA_Start function, the data
stored in this buffer will be the DO data.
handle: The handle of system DMA memory returned from system. Use this
handle in _7200_DI_DMA_Start or _7200_DO_DMA_Start.
buf_size: Bytes to allocate. Please be careful, the unit of this parameter is
BYTE, not SAMPLE.
actual_size: The actual size system allocate for DMA memory. The unit is
BYTE. If system is not able to get a block of contiguous memory of specified
buf_size, it will allocate a block of memory as large as it can. In this case,
this function returns ERR_SmallerDMAMemAllocated, and actual_size
denotes the actual size of allocated memory.
@ Return Code
ERR_NoError
ERR_SmallerDMAMemAllocated
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5.14 _7200_Free_DMA_Mem
@ Description
Releases system DMA memory. This function is only available in Windows
95/98.
@ Syntax
Visual C++ (Windows 95)
int W_7200_Free_DMA_Mem (U32 handle)
Visual Basic (Windows 95)
W_7200_Free_DMA_Mem (ByVal handle As Long ) As Long
@ Argument
handle: The handle of system DMA memory to release.
@ Return Code
ERR_NoError
5.15 _7200_Alloc_DBDMA_Mem
@ Description
Contact Windows 95/98 system to allocate a block of contiguous memory as
circular buffer for double-buffered DMA DI transfer. This function is only
available in Windows 95/98 version. For double-buffered transfering, please
refer to Section 6 “Double Buffered Mode Principle”.
@ Syntax
Visual C++ (Windows 95)
int W_7200_Alloc_DBDMA_Mem (U32 *buff,U32 *handle, U32
buf_size, U32 *actual_size)
Visual Basic (Windows 95)
W_7200_Alloc_DBDMA_Mem (buff As Long, handle As Long, ByVal
buf_size As Long, actual_size As Long) As Long
@ Argument
buff: There is a dummy buffer attached to the DMA memory this function will
allocate. But this buffer needs to have size equal to or more than buf_size
bytes.
handle: The handle of system DMA memory returned from system. Use this
handle in _7200_DI_DMA_Start.
buf_size: Bytes to allocate. This is the half size of circular buffer in byte.
That is, this is the size of each half buffer in byte.
actual_size: The actual DMA memory size system allocate for each half
buffer. If system is not able to get a block of contiguous memory of specified
buf_size, it will allocate a block of memory as large as it can. In this case,
this function returns ERR_SmallerDMAMemAllocated, and actual_size
46 C/C++ Libraries
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denotes the actual size of allocated memory for each half of circular buffer.
@ Return Code
ERR_NoError
ERR_SmallerDMAMemAllocated
5.16 _7200_Free_DBDMA_Mem
@ Description
Releases a system’s circular buffer DMA memory. This function is only
available in Windows 95/98. For double-buffered transfer principle, please
refer to Section 6 “Double Buffered Mode Principle”.
@ Syntax
Visual C++ (Windows 95)
int W_7200_Free_DBDMA_Mem (U32 handle)
Visual Basic (Windows 95)
W_7200_Free_DBDMA_Mem (ByVal handle As Long ) As Long
@ Argument
handle: The handle of system DMA memory to release.
@ Return Code
ERR_NoError
5.17 _7200_DI_DMA_Start
@ Description
The function will perform digital input N times with DMA data transfer by using
one of the following four sampling modes:
1. pacer trigger (internal timer trigger)
2. external rising edge I_REQ
3. external falling edge I_REQ
4. I_REQ & I_ACK handshaking
It will take place in the background which will not stop until the Nth input data is
transferred or your program execute _7200_DI_DMA_Stop function to stop
the process.
After executing this function, it is necessary to check the status of the
operation by using the function _7200_DI_DMA_Status. The PCI-7200 Bus
mastering DMA is different from traditional PC style DMA. Its description is as
follows:
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Bus Mastering DMA mode of the PCI-7200:
PCI bus mastering offers the highest possible speed available on the
PCI-7200. When the function _7200_DI_DMA_Start is executed, it will enable
PCI bus master operation. This is conceptually similar to DMA (Direct Memory
Access) transfers in a PC but it is really PCI bus mastering. It does not use an
8237-style DMA controller in the host computer and therefore isn't blocked in
64k max groups. PCI-7200 bus mastering works as follows:
1. To set up bus mastering, first do all normal PCI-7200 initialization necessary
to control the board in status mode. This includes testing for the presence of
the PCI BIOS, determining the base addresses, slot number, vendor and
device ID's, I/O, or memory, space allocation, etc. Please make sure the
PCI-7200 is plugged in a bus master slot, otherwise this function will not be
workable.
2. Load the PCI controller with the count and 32-bit physical address of the
start of previously allocated destination memory, which will accept data.
This count is the number of bytes (not long words) transferred during the bus
master operation and can be a large number up to 64 million (2^26) bytes.
Since PCI-7200 transfers are always long words, this equals 16 million long
words (2^24).
3. After the input sampling is started, the input data is stored in the FIFO of PCI
controller. Each bus mastering data transfer continually tests if any data in
the FIFO and then blocks transfer, the system will continuously loop until the
conditions are satisfied again but will not exit the block transfer cycle if the
block count is not complete. If there is momentarily no input data, the
PCI-7200 will relinquish the bus temporarily but returns immediately when
more input data appears. This operation continues until the whole block is
done.
4. This operation proceeds transparently until the PCI controller transfer byte
count is reached. All normal PCI bus operations applied here, such as a
receiver that cannot accept the transfers, higher priority devices requesting
the PCI bus, etc. Remember that only one PCI initiator can have bus
mastering at any one time. However, review the PCI priority and "fairness"
rules. Also study the effects of the Latency Timer. Additionaly, be aware that
the PCI priority strategy (round robin rotated, fixed priority, custom, etc.) is
unique to each host PC and is explicitly not defined by the PCI standard.
You must determine this priority scheme for your own PC (or replace it).
The interrupt request from the PCI controller can be optionally set up to
indicate that this loanword count is complete although this can also be
determined by polling the PCI controller.
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@ Syntax
Visual C++ (Windows 95)
int W_7200_DI_DMA_Start (U8 mode, U32 count, U32 handle,
Boolean wait_trg, U8 trg_pol, Boolean clear_fifo, Boolean
disable_di)
Visual Basic (Windows 95)
W_7200_DI_DMA_Start(ByValmodeAsByte, ByValcountAsLong,
ByVal handle As Long, ByVal wait_trg as Byte, ByVal trg_pol
As Byte, ByVal clear_fifo As Byte, ByVal disable_di As Byte)
As Long
C/C++ (DOS)
int _7200_DI_DMA_Start (U8 mode, U32 count, U32 *di_buffer,
Boolean wait_trig, U8 trig_pol, Boolean clear_fifo, Boolean
disable_di)
@ Argument
mode: Digital Input trigger modes
DI_MODE0: Internal timer pacer (TIME 0)
DI_MODE1: External signal I_REQ rising edge
DI_MODE2: External signal I_REQ falling edge
DI_MODE3: I_REQ & I_ACK handshaking
count: For non-double-buffered DI, this parameter denotes the number of
digital input samples to read. For double-buffered DI, it is the size of circular
buffer (in samples, not in bytes).
handle (Win95): The handle of system DMA memory. In Windows 95,
before calling _7200_DI_DMA_Start, depending on using double-buffer
mode
or
not,
either
_7200_Alloc_DMA_Mem
or
_7200_Alloc_DBDMA_Mem must be called to allocate a contiguous DMA
memory and get the handle.
di_buffer (DOS): If double buffer mode is disabled, this is the start address
of the memory buffer to store the DI data. If double buffer mode is enabled,
this memory buffer is actually of no use. But the buffer size still must be
larger than the number of count (count*4 bytes). Use this buffer as transfer
buffer in _7200_DblBufferTransfer to make use of this buffer.
**This memory should be double-word alignment.
wait_trig: The waiting status of trigger
DI_NONWAITING: the input sampling will be start immediately
DI_WAITING: the input samples waiting rising or falling edge trigger
to start DI
trig_pol: trigger polarity
DI_RISING: rising edge trigger
DI_FALLING: falling edge trigger
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clear_fifo:
0: retain the FIFO data
1: clear FIFO data before perform digital input
disable_di:
0: digital input operation still active after DMA transfer complete
1: disable digital input operation immediately when DMA transfer
complete
@ Return Code
ERR_NoError
ERR_BoardNoInit
ERR_InvalidDIOMode
ERR_InvalidDIOCnt
ERR_NotDWordAlign
ERR_DMATransferNotAllowed
5.18 _7200_DI_DMA_Status
@ Description
Since the _7200_DI_DMA_Start function is executed in background, users
can issue this function to check its operation status. This function only works
when double-buffer mode is set as disable.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DI_DMA_Status (U8 *status, U32 *count)
Visual Basic (Windows 95)
W_7200_AD_Status (status As Byte, count As Long ) As Long
C/C++ (DOS)
int _7200_AD_DMA_Status (U8 *status, U32 *count)
@ Argument
status:status of the DMA data transfer
0: DI_DMA_STOP: DMA is completed
1: DI_DMA_RUN: DMA is not completed
count: the numbers of DI data which has been transferred.
@ Return Code
ERR_NoError
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5.19 _7200_DI_DMA_Stop
@ Description
This function is used to stop the DMA data transferring. After executing this
function, the _7200_DI_DMA_Start function is stopped. The function returns
the number of the data which has been transferred, no matter if the digital
input DMA data transfer is stopped by this function or by the DMA terminal
count, ISR.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DI_DMA_Stop (U32 * count)
Visual Basic (Windows 95)
W_7200_DI_DMA_Stop ( count As Long ) As Long
C/C++ (DOS)
int _7200_DI_DMA_Stop (U32 *count)
@ Argument
count: the number of DI data which has been transferred.
@ Return Code
ERR_NoError
ERR_BoardNoInit
5.20 _7200_DblBufferMode
@ Description
This function is used to enable or disable double buffer mode for DMA DI
operation.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DblBufferMode (Boolean db_flag)
Visual Basic (Windows 95)
W_7200_DblBufferMode (ByVal db_flag As Byte) As Long
C/C++ (DOS)
int _7200_CheckHalfReady (Boolean db_flag)
@ Argument
db_flag:
1: double buffer mode enabled
0: double buffer mode disabled
@ Return Code
ERR_NoError
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5.21 _7200_CheckHalfReady
@ Description
When you use _7200_DI_DMA_Start to sample digital input data and
double buffer mode is set as enable. Users must use
_7200_CheckHalfReady to check data ready (data half full) or not in the
circular buffer, and using _7200_DblBufferTransfer to get data.
@ Syntax
Visual C++ (Windows 95)
int W_7200_CheckHalfReady (Boolean * halfReady)
Visual Basic (Windows 95)
W_7200_CheckHalfReady (halfReady As Byte) As Long
C/C++ (DOS)
int _7200_CheckHalfReady (Booelan *halfReady)
@ Argument
halfReady: 1 (TRUE) or 0 (FALSE)
@ Return Code
ERR_NoError
5.22 _7200_DblBufferTransfer
@ Description
Use this function to copy the input data in the circular buffer to the transfer
buffer. It copies half of the circular buffer, either first half or second half, to
the transfer buffer.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DblBufferTransfer (U32 *userBuffer)
Visual Basic (Windows 95)
W_7200_DblBufferTransfer (userBuffer As Long) As Long
C/C++ (DOS)
int _7200_DblBufferTransfer (U32 *userBuffer)
@ Argument
userBuffer: the start address of the transfer buffer. The
W_7200_DblBufferTransfer function copies half of the circular buffer to
userBuffer.
@ Return Code
ERR_NoError, ERR_NotHalfReady
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5.23 _7200_GetOverrunStatus
@ Description
When using _7200_DI_DMA_Start to convert Digital I/O data with double
buffer mode enabled, and not using _7200_DblBufferTransfer to move
converted data then double buffer overrun will occur. Use this function to
check overrun count.
@ Syntax
Visual C++ (Windows 95)
int W_7200_GetOverrunStatus (U32 * overrunCount)
Visual Basic (Windows 95)
int W_7200_GetOverrunStatus (overrunCount As Long) As Long
C/C++ (DOS)
int _7200_GetOverrunStatus (U32 *overrunCount )
@ Argument
overrunCount: number of overruns.
@ Return Code
ERR_NoError
5.24 _7200_DO_DMA_Start
@ Description
The function will perform digital output N times with DMA data transfer by
using the following four sampling modes:
1. Pacer trigger (internal timer trigger, TIME 1)
2. Internal timer pacer with O_REQ enabled
3. O_REQ & O_ACK handshaking
It takes place in the background which will not be stop until the Nth
conversion has been completed or the program executes the
_7200_DO_DMA_Stop function to stop the process. After executing this
function, it is necessary to check the status of the operation by using the
function _7200_DO_DMA_Status.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DO_DMA_Start (U8 mode, U32 count, U32 handle,
Boolean repeat)
Visual Basic (Windows 95)
W_7200_DO_DMA_Start(ByValmodeAsByte, ByValcountAsLong,
ByVal handle As Long, ByVal repeat as Byte) As Long
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C/C++ (DOS)
int _7200_DO_DMA_Start (U8 mode, U32 count, U32 *do_buffer,
Boolean repeat)
@ Argument
mode: Digital output trigger modes
DO_MODE_0: Internal timer pacer (TIME 1)
DO_MODE_1: Internal timer pacer with O_REQ enable
DO_MODE_2: O_REQ & I_REQ handshaking
count: the sample number of digital output data (in samples, not in bytes)
handle (Win 95): the handle of system DMA memory. In Windows 95,
before calling W_7200_DO_DMA_Start, W_7200_Alloc_DMA_Mem must
be called to allocate a contiguous DMA memory and get the handle of it.
Also W_7200_Alloc_DMA_Mem will attach a buffer to DMA memory. The
DO data is stored in the buffer attached to this handle.
do_buffer (DOS): the start address of the memory buffer to store the DO
data.
** This memory should be double-word alignment
repeat: The digital output will be continuous or only one shot.
CONTINUOUS:
_7200_DO_DMA_STOP is called.
ONE_SHOT : digital output only one-shot.
@ Return Code
digital
output
will
be
continuous
until
ERR_NoError
ERR_InvalidDIMode
ERR_InvalidBoardNumber
ERR_BoardNoInit
ERR_InvalidDIOCnt
ERR_NotDWordAlign
ERR_DMATransferNotAllowed
5.25 _7200_DO_DMA_Status
@ Description
Since the _7200_DO_DMA_Start function is executed in background, users
can issue the function _7200_DO_DMA_Status to check its operation
status.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DO_DMA_Status (U8 *status, U32 * count)
Visual Basic (Windows 95)
W_7200_DO_Status ( status As Byte, count As Long ) As Long
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C/C++ (DOS)
int _7200_DO_DMA_Status (U8 *status , U32 *count)
@ Argument
status: status of the DMA data transfer.
0: DO_DMA_STOP: DMA is completed
1: DO_DMA_RUN: DMA is not completed
count: the amount of DO data which has been transferred.
@ Return Code
ERR_NoError
5.26 _7200_DO_DMA_Stop
@ Description
This function is used to stop the DMA DO operation. After executing this
function, the _7200_DO_DMA_Start function is stopped. The function
returns the number of the data which has been transferred, regardless if the
digital output DMA data transfer is stopped by this function or by the DMA
terminal count ISR.
@ Syntax
Visual C++ (Windows 95)
int W_7200_DO_DMA_Stop (U32 *count)
Visual Basic (Windows 95)
W_7200_DO_DMA_Stop (count As Long) As Long
C/C++ (DOS)
int _7200_DO_DMA_Stop (U32 *count)
@ Argument
count: the number of digital output data which has been transferred.
@ Return Code
ERR_NoError
ERR_BoardNoInit
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5.27 _7200_DI_Timer
@ Description
This function is used to set the internal timer pacer for digital input. There are
two configurations for the internal timer pacer:
1. Non-cascaded (One COUNTER 0 only)
8254 Timer/Counter
4MHz Input
Counter 0
CLK0
GATE0
OUT0
Digital Input Trigg
Timer pacer frequency = 4Mhz / C0
2. Cascaded (TIME2 cascaded with COUNTER0)
8254 Timer/Counter
Counter 0
CLK0
GATE0
OUT0
Digital Input Trigg
Counter 1
CLK1
GATE1
OUT1
4MHz Input
Counter 2
CLK2
OUT2
GATE2
Timer pacer frequency = 4Mhz / (C0 * C2)
@ Syntax
Visual C++ (Windows 95)
int W_7200_DI_Timer (U16 c0, U16 c2, Boolean mode)
Visual Basic (Windows 95)
W_7200_DI_Timer ( ByVal c0 As Integer, ByVal c2 As Integer,
ByVal mode As Byte ) As Long
C/C++ (DOS)
int _7200_DI_Timer (U16 c0, U16 c2, Boolean mode)
@ Argument
c0: frequency divider of Counter #0. Valid value ranges from 2 to 65535.
c2: frequency divider of Counter #2. Valid value ranges from 2 to 65535.
Note: Since the Integer type in Visual Basic is a signed integer. Its range is
within -32768 and 32767. In Visual Basic, to set c0 or c2 to a value
larger than 32767, set it as the intended value minus 65536. For
example, to set c0 as 40000, set c0 as 40000-65536=-25536.
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mode: TIMER_NONCASCADE or TIMER_CASCADE
@ Return Code
ERR_NoError
ERR_InvalidBoardNumber
ERR_InvalidTimerMode
ERR_BoardNoInit
5.28 _7200_DO_Timer
@ Description
This function is used to set the internal timer pacer for digital output. There
are two configurations for the internal timer pacer:
1. Non-cascaded (One COUNTER 0 only)
8254 Timer/Counter
4MHz Input
Counter 1
CLK0
GATE0
OUT0
Digital Output Trigg
Timer pacer frequency = 4Mhz / C1
2. Cascaded (TIME2 cascaded with COUNTER0)
8254 Timer/Counter
Counter 0
CLK0
GATE0
OUT0
Counter 1
CLK1
GATE1
OUT1
Digital Input Trigg
4MHz Input
Counter 2
CLK2
OUT2
GATE2
Timer pacer frequency = 4Mhz / (C1 * C2)
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@ Syntax
Visual C++ (Windows 95)
int W_7200_DO_Timer (U16 c1, U16 c2, Booelan mode)
Visual Basic (Windows 95)
W_7200_DO_Timer (ByVal c1 As Integer, ByVal c2 As Integer,
ByVal mode As Byte) As Long
C/C++ (DOS)
int _7200_DO_Timer (U16 c1, U16 c2, Boolean mode)
@ Argument
c1 : frequency divider of Counter #1
c2 : frequency divider of Counter #2
Note : Since the Integer type in Visual Basic is a signed integer. Its range is
within -32768 and 32767. In Visual Basic, to set c1 or c2 to a value
larger than 32767, set it as the intended value minus 65536. For
example, to set c0 as 40000, set c0 as 40000-65536=-25536.
mode: TIMER_NONCASCADE or TIMER_CASCADE
@ Return Code
ERR_NoError
ERR_InvalidBoardNumber
ERR_InvalidTimerMode
ERR_BoardNoInit
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6
Double Buffer Mode Principle
The data buffer for a double-buffered DMA DI operation is logically a circular
buffer divided into two equal halves. The double-buffered DI begins when the
device starts writing data into the first half of the circular buffer (Figure 6-1a).
After device begins writing to the second half of the circular buffer, users can
copy the data from the first half into the transfer buffer (Figure 6-1b). Users
now can process the data in the transfer buffer according to application needs.
After the board has filled the second half of the circular buffer, the board
returns to the first half buffer and overwrites the old data. Users now can copy
the second half of the circular buffer to the transfer buffer (Figure 6-1c). The
data in the transfer buffer is again available for process. The process can be
repeated endlessly to provide a continuous stream of data to applications
(Figure 6-1d).
a
b
Incoming DMA
input data
>
> >
Circular Buffer
Transfer Buffer
c
d
>
>
>
>
> > >
Empty Buffer
Untransferred Data
Transferred Data
Figure 6-1
Double Buffer Mode Principle 59
•
The PCI-7200 double buffer mode functions were designed according to the
principle described above. If using _7200_DblBufferMode() to enable double
buffer mode, _7200_DI_DMA_Start() will perform double-buffered DMA DI.
Call _7200_CheckHalfReady() to check if data in the circular buffer is half-full
and ready for copying to the transfer buffer. Then call
_7200_DblBufferTransfer() to copy data from the ready half buffer to the
transfer buffer.
In Windows 95, W_7200_Alloc_DBDMA_Mem() is needed to allocates a
contiguous DMA memory for the circular buffer. The buf_size argument of
W_7200_Alloc_DBDMA_Mem() is the half size of circular buffer in byte, that is,
the size of each half buffer in byte. The DMA memory is referenced by the
return parameter handle. This memory is system memory; users are not
allowed to access it directly.
60 Double Buffer Mode Principle
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7
Limitations
The 12MB/sec data transfer rate can only be possibly achieved in systems
where the PCI-7200 card is the only device using the bus, but the speed can
not be guaranteed due to the limited FIFO depth.
The PCI-7200 supports three input clock modes, internal clock, external clock,
and handshaking modes. The first two modes cannot guarantee the input data
integrity in high-speed data rate because of the limited FIFO depth and
PCI-bus latency variation. The handshaking mode is the only mode that data
integrity can be guaranteed. During handshaking, expect 12 MB/sec data rate
on average, but the speed is not guaranteed.
The guaranteed data rate with internal clock or external clock mode is
1MB/sec on systems where PCI-7200 card is the only device using the bus.
The largest transfer size (in bytes) PCI-7200 can perform is 64MB.
Limitations 61
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Warranty Policy
Thank you for choosing ADLINK. To understand your rights and enjoy all the
after-sales services we offer, please read the following carefully:
1.
Before using ADLINK’s products please read the user manual and follow
the instructions exactly.
2.
3.
When sending in damaged products for repair, please attach an RMA
application form.
All ADLINK products come with a two-year guarantee, repaired free of
charge.
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•
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The warranty period starts from the product’s shipment date from
ADLINK’s factory.
Peripherals and third-party products not manufactured by ADLINK
will be covered by the original manufacturers’ warranty.
End users requiring maintenance services should contact their local
dealers. Local warranty conditions will depend on local dealers.
4.
This warranty will not cover repair costs due to:
a. Damage caused by not following instructions.
b. Damage caused by carelessness on the users’ part during product
transportation.
c. Damage caused by fire, earthquakes, floods, lightening, pollution,
other acts of God, and/or incorrect usage of voltage transformers.
d. Damage caused by unsuitable storage environments (i.e. high
temperatures, high humidity, or volatile chemicals.
e. Damage caused by leakage of battery fluid.
f. Damage from improper repair by unauthorized technicians.
g. Products with altered and/or damaged serial numbers.
h. Other categories not protected under our guarantees.
5.
6.
Customers are responsible for shipping costs to transport damaged
products to our company or sales office.
To ensure the speed and quality of product repair, please download a
Damaged products with attached RMA forms receive priority.
For further questions, please contact our FAE staff.
ADLINK: [email protected]
Product Warranty/Service 63
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